Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT JUSTIFIED MODE
- LEFT JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- MICBIAS GENERATION
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH POWER OUTPUT DRIVERS
- SHORT CIRCUIT OUTPUT PROTECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC32
SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 .............................................................................................................................................
www.ti.com
Page 0 / Register 32: Left AGC Gain Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R 00000000 Left Channel Gain Applied by AGC Algorithm
11101000: Gain = – 12.0-dB
11101001: Gain = – 11.5-dB
11101010: Gain = – 11.0-dB
…
00000000: Gain = 0.0-dB
00000001: Gain = +0.5-dB
…
01110110: Gain = +59.0-dB
01110111: Gain = +59.5-dB
Page 0 / Register 33: Right AGC Gain Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D0 R 00000000 Right Channel Gain Applied by AGC Algorithm
11101000: Gain = – 12.0-dB
11101001: Gain = – 11.5-dB
11101010: Gain = – 11.0-dB
…
00000000: Gain = 0.0-dB
00000001: Gain = +0.5-dB
…
01110110: Gain = +59.0-dB
01110111: Gain = +59.5-dB
Page 0 / Register 34: Left AGC Noise Gate Debounce Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D3 R/W 00000 Left AGC Noise Detection Debounce Control
These times
(1)
will not be accurate when double rate audio mode is enabled.
00000: Debounce = 0-msec
00001: Debounce = 0.5-msec
00010: Debounce = 1-msec
00011: Debounce = 2-msec
00100: Debounce = 4-msec
00101: Debounce = 8-msec
00110: Debounce = 16-msec
00111: Debounce = 32-msec
01000: Debounce = 64 × 1 = 64ms
01001: Debounce = 64 × 2 = 128ms
01010: Debounce = 64 × 3 = 192ms
…
11110: Debounce = 64 × 23 = 1472ms
11111: Debounce = 64 × 24 = 1536ms
D2 – D0 R/W 000 Left AGC Signal Detection Debounce Control
These times
(1)
will not be accurate when double rate audio mode is enabled.
000: Debounce = 0-msec
001: Debounce = 0.5-msec
010: Debounce = 1-msec
011: Debounce = 2-msec
100: Debounce = 4-msec
101: Debounce = 8-msec
110: Debounce = 16-msec
111: Debounce = 32-msec
(1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled
50 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC32