Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT JUSTIFIED MODE
- LEFT JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- MICBIAS GENERATION
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH POWER OUTPUT DRIVERS
- SHORT CIRCUIT OUTPUT PROTECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
TLV320AIC32
www.ti.com
............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
Page 0 / Register 18: MIC3L/R to Right ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D4 R/W 1111 MIC3L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = – 1.5-dB
0010: Input level control gain = – 3.0-dB
0011: Input level control gain = – 4.5-dB
0100: Input level control gain = – 6.0-dB
0101: Input level control gain = – 7.5-dB
0110: Input level control gain = – 9.0-dB
0111: Input level control gain = – 10.5-dB
1000: Input level control gain = – 12.0-dB
1001 – 1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the right ADC PGA
D3 – D0 R/W 1111 MIC3R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = – 1.5-dB
0010: Input level control gain = – 3.0-dB
0011: Input level control gain = – 4.5-dB
0100: Input level control gain = – 6.0-dB
0101: Input level control gain = – 7.5-dB
0110: Input level control gain = – 9.0-dB
0111: Input level control gain = – 10.5-dB
1000: Input level control gain = – 12.0-dB
1001 – 1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to right ADC PGA
Page 0 / Register 19: LINE1L to Left ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved. Write Only zero to this bit.
D6 – D3 R/W 1111 LINE1L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the left ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = – 1.5-dB
0010: Input level control gain = – 3.0-dB
0011: Input level control gain = – 4.5-dB
0100: Input level control gain = – 6.0-dB
0101: Input level control gain = – 7.5-dB
0110: Input level control gain = – 9.0-dB
0111: Input level control gain = – 10.5-dB
1000: Input level control gain = – 12.0-dB
1001 – 1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the left ADC PGA
D2 R/W 0 Left ADC Channel Power Control
0: Left ADC channel is powered down
1: Left ADC channel is powered up
D1 – D0 R/W 00 Left ADC PGA Soft-Stepping Control
00: Left ADC PGA soft-stepping at once per Fs
01: Left ADC PGA soft-stepping at once per two Fs
10 – 11: Left ADC PGA soft-stepping is disabled
Page x / Register 20: LINE2L to Left
(1)
ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved. Write only zero to this bit.
(1) LINE1R SEvsFD control is available for both left and right channels. However this setting must be same for both the channels.
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