Datasheet

TLV320AIC32
www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
Page 0 / Register 1: Software Reset Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 W 0 Software Reset Bit
0 : Don ’ t Care
1 : Self clearing software reset
D6 – D0 W 0000000 Reserved; don ’ t write
Page 0 / Register 2: Codec Sample Rate Select Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D4 R/W 0000 ADC Sample Rate Select
0000: ADC Fs = Fsref/1
0001: ADC Fs = Fsref/1.5
0010: ADC Fs = Fsref/2
0011: ADC Fs = Fsref/2.5
0100: ADC Fs = Fsref/3
0101: ADC Fs = Fsref/3.5
0110: ADC Fs = Fsref/4
0111: ADC Fs = Fsref/4.5
1000: ADC Fs = Fsref/5
1001: ADC Fs = Fsref/5.5
1010: ADC Fs = Fsref / 6
1011 – 1111: Reserved, do not write these sequences.
Note: ADC sample rate must be programmed to same value as DAC sample rate
D3-D0 R/W 0000 DAC Sample Rate Select
0000 : DAC Fs = Fsref/1
0001 : DAC Fs = Fsref/1.5
0010 : DAC Fs = Fsref/2
0011 : DAC Fs = Fsref/2.5
0100 : DAC Fs = Fsref/3
0101 : DAC Fs = Fsref/3.5
0110 : DAC Fs = Fsref/4
0111 : DAC Fs = Fsref/4.5
1000 : DAC Fs = Fsref/5
1001: DAC Fs = Fsref/5.5
1010: DAC Fs = Fsref / 6
1011 – 1111 : Reserved, do not write these sequences.
Page 0 / Register 3: PLL Programming Register A
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PLL Control Bit
0: PLL is disabled
1: PLL is enabled
D6 – D3 R/W 0010 PLL Q Value
0000: Q = 16
0001 : Q = 17
0010 : Q = 2
0011 : Q = 3
0100 : Q = 4
…
1110: Q = 14
1111: Q = 15
D2 – D0 R/W 000 PLL P Value
000: P = 8
001: P = 1
010: P = 2
011: P = 3
100: P = 4
101: P = 5
110: P = 6
111: P = 7
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