Datasheet

N-1 N-2 1 0 N-1 N-2 1 0
word
clock
bit clock
data
in/out
RightChannelData
RightChannelData
LeftChannelData
LeftChannelData
N-1 N-2 1 0 N-1 N-2 1 0
word
clock
bit clock
data
in/out
DSP Mode
LeftJustifiedMode
offset
offset
offset
AUDIO DATA CONVERTERS
AUDIO CLOCK GENERATION
TLV320AIC32
www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
Figure 24. DSP Mode and Left Justified Modes, Showing the
Effect of a Programmed Data Word Offset
The TLV320AIC32 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations, which are described further below.
The data converters are based on the concept of an Fsref rate that is used internal to the part, and it is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, Fsref will be
either 44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with
additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and
DAC, and also to enable high quality playback of low sampling rate data, without high frequency audible noise
being generated.
The sampling rate of the ADC and DAC can be set to Fsref/NDAC or 2 × Fsref/NDAC, with NDAC being 1, 1.5, 2,
2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6.
The audio converters in the TLV320AIC32 need an internal audio master clock at a frequency of 256 × Fsref,
which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC32 is shown in Figure 25 .
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