Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION
- DEVICE INFORMATION
- ABSOLUTE MAXIMUM RATINGS
- DISSIPATION RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- OVERVIEW
- HARDWARE RESET
- DIGITAL CONTROL SERIAL INTERFACE
- I2C CONTROL INTERFACE
- DIGITAL AUDIO DATA SERIAL INTERFACE
- RIGHT JUSTIFIED MODE
- LEFT JUSTIFIED MODE
- I2S MODE
- DSP MODE
- TDM DATA TRANSFER
- AUDIO DATA CONVERTERS
- AUDIO CLOCK GENERATION
- STEREO AUDIO ADC
- AUTOMATIC GAIN CONTROL (AGC)
- STEREO AUDIO DAC
- DIGITAL AUDIO PROCESSING
- DIGITAL INTERPOLATION FILTER
- DELTA-SIGMA AUDIO DAC
- AUDIO DAC DIGITAL VOLUME CONTROL
- ANALOG OUTPUT COMMON-MODE ADJUSTMENT
- AUDIO DAC POWER CONTROL
- AUDIO ANALOG INPUTS
- ANALOG INPUT BYPASS PATH FUNCTIONALITY
- ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
- INPUT IMPEDANCE AND VCM CONTROL
- PASSIVE ANALOG BYPASS DURING POWER DOWN
- MICBIAS GENERATION
- ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
- ANALOG HIGH POWER OUTPUT DRIVERS
- SHORT CIRCUIT OUTPUT PROTECTION
- CONTROL REGISTERS
- Output Stage Volume Controls
RIGHT JUSTIFIED MODE
BCLK
WCLK
SDIN/
SDOUT
1 00 1 0
1/fs
LSBMSB
LeftChannel RightChannel
2 2
n−1
n−3
n−2
n−1
n−3
n−2
LEFT JUSTIFIED MODE
n-1 n-2 n-3 n-1 n-2 n-3
I2S MODE
TLV320AIC32
www.ti.com
............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC32 further includes programmability to tri-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to
use a single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface will be put into a tri-state output condition.
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 20. Right Justified Serial Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
Figure 21. Left Justified Serial Data Bus Mode Operation
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
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