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Table Of Contents

FEATURES

DESCRIPTION

TLV320AIC32

www.ti.com

............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008

Low-Power Stereo Audio CODEC for Portable Audio/Telephony

• Low Power: 14-mW Stereo, 48-kHz Playback

With 3.3-V Analog Supply

• Stereo Audio DAC

• Programmable Input/Output Analog Gains

– 100 dB A Signal-to-Noise Ratio

• Automatic Gain Control (AGC) for Record

– 16/20/24/32-Bit Data

• Programmable Microphone Bias Level

– Supports Rates From 8 kHz to 96 kHz

• Programmable PLL for Flexible Clock

– 3D/Bass/Treble/EQ/De-Emphasis Effects

Generation

• Stereo Audio ADC

• I

C Control Bus

– 92 dB A Signal-to-Noise Ratio

• Audio Serial Data Bus Supports I

– Supports Rates From 8 kHz to 96 kHz

Left/Right-Justified, DSP, and TDM Modes

• Six Audio Input Pins

• Extensive Modular Power Control

– Six Stereo Single-Ended Inputs

• Power Supplies:

• Six Audio Output Drivers

– Analog: 2.7 V – 3.6 V

– Stereo 8- Ω , 500 mw/Channel Speaker Drive

– Digital Core: 1.65 V – 1.95 V

Capability

– Digital I/O: 1.1 V – 3.6 V

– Stereo Fully-Differential or Single-Ended

• Available Packages: 5 × 5 mm, 32-Pin QFN

Headphone Drivers

– Fully Differential Stereo Line Outputs

The TLV320AIC32 is a low-power stereo-audio codec with a stereo headphone amplifier, as well as multiple

inputs and outputs, programmable in single-ended or fully-differential configurations. Extensive register- based

power control is included, enabling stereo 48-kHz DAC playback as low as 14 mW from a 3.3-V analog supply,

making it ideal for portable, battery-powered audio and telephony applications.

The record path of the TLV320AIC32 contains integrated microphone bias, digitally-controlled stereo-microphone

pre-amp, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. The

playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable

volume controls, to the various outputs.

The TLV320AIC32 contains four high-power output drivers as well as two fully differential output drivers. The

high-power output drivers are capable of driving a variety of load configurations, including up to four channels of

single-ended 16- Ω headphones using ac-coupling capacitors, or stereo 16- Ω headphones in a cap-less output

configuration. In addition, pairs of drivers can be used to drive 8- Ω speakers in a BTL configuration at 500 mW

per channel.

The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering

in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32 kHz, 44.1

kHz, and 48 kHz rates. The stereo-audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by

programmable gain amplifiers providing up to +59.5 dB analog gain for low-level microphone inputs.

The serial control bus supports the I

C protocol, while the serial-audio data bus is programmable for I

S, left/right

justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support

for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with special

attention paid to the most popular cases of 12 MHz, 13 MHz, 16 MHz, 19.2 MHz, and 19.68 MHz system clocks.

The TLV320AIC32 operates from an analog supply of 2.7 V – 3.6 V, a digital core supply of 1.65 V – 1.95 V, and

a digital I/O supply of 1.1 V – 3.6 V. The device is available in a 5 × 5 mm, 32-lead QFN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (81 pages)

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TLV320AIC32 www.ti.com .............................................................................................................................................
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com WCLK DIN DOUT BCLK DVDD DVSS IOVDD AVSS_ADC AVDD_DAC AVSS_DAC DRVDD DRVSS DRVDD SIMPLIFIED BLOCK DIAGRAM + HPL+ Audio Serial Bus Voltage Supplies MIC2/LINE2L VCM HPL-/HPLCOM + MIC3/LINE3L MIC1/LINE1L MIC1/LINE1R + PGA 0/+59.5dB 0.5dB steps + PGA 0/+59.5dB 0.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 DEVICE INFORMATION PIN ASSIGNMENTS 1 8 32 9 TLV320AIC32 25 16 24 17 Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME QFN NO.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Table 1. TERMINAL FUNCTIONS (continued) TERMINAL DESCRIPTION NAME QFN NO.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL I/O VIL Input low level IIL = +5-µA –0.3 VIH Input high level (5) IIH = +5-µA 0.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) BCLK td(DO-WS) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK td(WS) td(WS) BCLK td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0146-01 PARAMETER IOVDD = 1.1 V MIN MAX IOVDD = 3.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) th(WS) tH(BCLK) BCLK td(DO-WS) tL(BCLK) td(DO-BCLK) SDOUT tS(DI) th(DI) SDIN T0145-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 All specifications at 25°C, DVDD = 1.8 V. WCLK tS(WS) tS(WS) th(WS) th(WS) tL(BCLK) BCLK td(DO-BCLK) tH(BCLK) SDOUT tS(DI) th(DI) SDIN T0146-02 PARAMETER IOVDD = 1.1 V MIN IOVDD = 3.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS -20 -30 -30 Capless, VDD = 3.6 V -40 Total Harmonic Distortion Total Harmonic Distortion - dB -20 AC-Coupled, VDD = 2.7 V -50 AC-Coupled, VDD = 3.6 V -60 -70 Capless, VDD = 2.7 V -80 -90 0.015 0.02 0.025 0.03 0.035 0.04 Power - W AC-Coupled, VDD = 2.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) 0 -20 -40 dB -60 -80 -100 -120 -140 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency - kHz Figure 9. Line Input to ADC FFT Plot -10.00 -20.00 -30.00 VDD = 2.7 V VDD = 3.3 V VDD = 3.6 V THD -40.00 -50.00 -60.00 -70.00 -80.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) 38 36 SNR - dB 34 32 30 28 26 0 10 20 30 40 50 60 PGA Gain Setting - dB Figure 11. ADC SNR vs PGA Gain Setting, –65 dBFS Input 1.20 1.10 Gain Error - dB 1.00 0.90 0.80 0.70 0.60 Left ADC Right ADC 0.50 0.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 Micbias - V TYPICAL CHARACTERISTICS (continued) 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 MICBIAS=AVDD MICBIAS=2.5V MICBIAS=2.0V 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 AVDD - V Figure 13. MICBIAS Output Voltage vs AVDD 3.2 MICBIAS=AVDD 3 Micbias - V 2.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) TYPICAL CIRCUIT CONFIGURATION IOVDD DSP or Apps Processor 2 kW SCL SDA MICBIAS /RESET Rp AVDD_DAC DRVDD DRVDD 0.1 mF MIC1L/LINE1L LINE_L 0.1mF 1mF 0.1mF 0.1mF A 0.47 mF FM Tuner AVDD (2.7V-3.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) IOVDD DSP or Apps Processor 2 kW SCL SDA MICBIAS /RESET Rp AVDD (2.7V-3.6V) MCLK BCLK WCLK DOUT DIN Rp AVDD_DAC DRVDD DRVDD 0.1 mF MIC1L/LINE1L 0.1 mF 0.1 mF 0.1 mF A 0.47 mF MIC2L/LINE2L MIC2R/LINE2R 0.47 mF 0.47 mF IOVDD AIC32 1.65-1.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com OVERVIEW The TLV320AIC32 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 SDA tHD-STA ³ 2.0 ms SCL tSU-STA ³ 2.0 ms tSU-STO ³ 2.0 ms tHD-STA ³ 2.0 ms S Sr P S T0114-02 2 Figure 17. I C Interface Timing Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com The TLV320AIC32 also responds to and acknowledges a General Call, which consists of the master issuing a command with a slave address byte of 00H.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC32 further includes programmability to tri-state the DOUT line during all bit clocks when valid data is not being sent.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com n-1 n-2 n-3 n-1 n-2 n-3 Figure 22. I2S Serial Data Bus Mode Operation DSP MODE In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 DSP Mode word clock bit clock data in/out N-1 N-2 1 Left Channel Data offset 0 N-1 N-2 1 0 Right Channel Data Left Justified Mode word clock bit clock data in/out N-1 offset N-2 1 Left Channel Data 0 N-1 offset N-2 1 0 Right Channel Data Figure 24.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com MCLK BCLK PLL_CLKIN CLKDIV_CLKIN CLKDIV_IN Q=2,3,…..,16,17 PLL_IN 2/Q K = J.D J = 1,2,3,…..,62,63 D= 0000,0001,….,9998,9999 R= 1,2,3,4,….,15,16 P= 1,2,….,7,8 K*R/P CLKDIV_OUT PLL_OUT 1/8 PLLDIV_OUT CODEC_CLKIN CODEC_CLK=256*Fsref CODEC DAC_FS ADC_FS WCLK= Fsref/Ndac Ndac=1,1.5,2,…..
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 When the PLL is enabled, Fsref = (PLLCLK_IN × K × R) / (2048 × P), where P = 1, 2, 3,…, 8 R = 1, 2, …, 16 K = J.D J = 1, 2, 3, …, 63 D = 0000, 0001, 0002, 0003, …, 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4 P, R, J, and D are register programmable.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve Fsref = 44.1 kHz or 48 kHz. Fsref = 44.1 kHz MCLK (MHz) P R J D ACHIEVED FSREF % ERROR 2.8224 1 1 32 0 44100.00 0.0000 5.6448 1 1 16 0 44100.00 0.0000 12.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Input Signal Output Signal AGC Gain Decay Time Attack Time Figure 26. Typical Operation of the AGC Algorithm During Speech Recording Note that the time constants here are correct when the ADC is not in double-rate audio mode.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 H(z) + N0 ) N1 z *1 32768 * D1 z *1 (1) where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients that should be loaded to implement standard de-emphasis filters are given in Table 2. Table 2.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Table 3.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 DELTA-SIGMA AUDIO DAC The stereo audio DAC incorporates a third order multi-bit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com AUDIO DAC POWER CONTROL The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can be powered up or down independently. This provides power savings when only a mono playback stream is needed.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ANALOG INPUT BYPASS PATH FUNCTIONALITY The TLV320AIC3105 includes the additional ability to route some analog input signals past the integrated data converters, for mixing with other analog signals and then direction connection to the output drivers.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com In general, connecting two switches to the same output pin should be avoided, as this error shorts two input signals together, which would likely cause distortion of the signal as the two signal are in contention. Poor frequency response would also likely occur.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS The TLV320AIC32 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 31 and Figure 32.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com LINE2L/MIC2L 0dB to -78dB LINE2R/MIC2R 0dB to -78dB PGA_L 0dB to -78dB + PGA_R 0dB to -78dB DAC_L1 0dB to -78dB DAC_R1 0dB to -78dB Figure 32.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 5. driving stereo headphones in single-ended configuration with two drivers, while the remaining two drivers are connected in BTL configuration to an 8-Ω speaker.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com The high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 Page 0 / Register 12: Audio Codec Digital Filter Control Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D6 R/W 00 Left ADC Highpass Filter Control 00: Left ADC highpass filter disabled 01: Left ADC highpass filter –3-dB frequency = 0.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 0 / Register 15: BIT READ/ WRITE RESET VALUE D6-D0 R/W 0000000 Left ADC PGA Gain Control Register (continued) DESCRIPTION Left ADC PGA Gain Setting 0000000: Gain = 0.0-dB 0000001: Gain = 0.5-dB 0000010: Gain = 1.0-dB … 1110110: Gain = 59.0-dB 1110111: Gain = 59.5-dB 1111000: Gain = 59.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 Page 0 / Register 18: BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D4 R/W 1111 MIC3L Input Level Control for Right ADC PGA Mix Setting the input level control to a gain below automatically connects MIC3L to the right ADC PGA mix 0000: Input level control gain = 0.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 0 / Register 32: BIT READ/ WRITE RESET VALUE D7–D0 R 00000000 DESCRIPTION Left Channel Gain Applied by AGC Algorithm 11101000: Gain = –12.0-dB 11101001: Gain = –11.5-dB 11101010: Gain = –11.0-dB … 00000000: Gain = 0.0-dB 00000001: Gain = +0.5-dB … 01110110: Gain = +59.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 Page 0 / Register 35: (1) Right AGC Noise Gate Debounce Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7–D3 R/W 00000 Right AGC Noise Detection Debounce Control These times (1) will not be accurate when double rate audio mode is enabled. 00000: Debounce = 0-msec 00001: Debounce = 0.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 0 / Register 43: BIT READ/ WRITE RESET VALUE D7 R/W 1 D6–D0 R/W Left DAC Digital Volume Control Register DESCRIPTION Left DAC Digital Mute 0: The left DAC channel is not muted 1: The left DAC channel is muted 0000000 Left DAC Digital Volume Control Setting 0000000: Gain = 0.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 Table 5. Output Stage Volume Control Settings and Gains (continued) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) Gain Setting Analog Gain (dB) 15 -7.5 45 -22.6 75 -37.7 105 -52.7 16 -8.0 46 -23.1 76 -38.2 106 -53.7 17 -8.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 0 / Register 86: LEFT_LOP/M Output Level Control Register BIT READ/ WRITE RESET VALUE DESCRIPTION D7-D4 R/W 0000 D3 R/W 0 LEFT_LOP/M Mute 0: LEFT_LOP/M is muted 1: LEFT_LOP/M is not muted D2 R/W 0 Reserved. Write only zero to this register bit.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 0 / Register 94: Module Power Status Register (continued) BIT READ/ WRITE RESET VALUE DESCRIPTION D1 R/W 0 HPROUT Driver Power Status 0: HPROUT Driver is not fully powered up 1: HPROUT Driver is fully powered up D0 R 0 Reserved. Do not write to this register bit.
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TLV320AIC32 SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 ............................................................................................................................................. www.ti.com Page 1 / Register 0: BIT READ/ WRITE RESET VALUE D7-D1 X 0000000 D0 R/W 0 DESCRIPTION Reserved, write only zeros to these register bits Page Select Bit Writing zero to this bit sets Page-0 as the active page for following register accesses.
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TLV320AIC32 www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008 Page 1 / Register 55–127: BIT READ/ WRITE RESET VALUE D7-D0 R 0x00 Reserved Registers DESCRIPTION Reserved. Do not write to these registers.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC32IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC32IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC32IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TLV320AIC32IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.