Datasheet

TLV320AIC3256
www.ti.com SLOS630B –DECEMBER 2010–REVISED JANUARY 2013
Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
AVdd to AVss –0.3 to 2.2 V
DVdd to DVss –0.3 to 2.2 V
Vsys to DVss –0.3 to 5.5 V
IOVdd to IOVss –0.3 to 3.9 V
Digital Input voltage IOVss to IOVdd + 0.3 V
Analog input voltage AVss to AVdd + 0.3 V
Operating temperature range –40 to 85 °C
Storage temperature range –55 to 150 °C
Junction temperature (T
J
Max) 105 °C
QFN package (RSB) Power dissipation (T
J
Max – TA) / θ
JA
W
θ
JA
Thermal impedance 35 C/W
WCSP package (YZF) Power dissipation (T
J
Max – TA) / θ
JA
W
θ
JA
Thermal impedance 50 C/W
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM MAX UNIT
AVdd Power Supply Voltage Range Referenced to AVss
(1)
1.5 1.8 1.95 V
IOVdd Referenced to IOVss
(1)
1.1 3.6
Vsys Referenced to DVss
(1)
1.5 1.8 5.5
DVdd
(2)
Referenced to DVss
(1)
1.26 1.8 1.95
DVdd_CP Power Supply Voltage Range Referenced to DVss
(1)
1.26 1.8 1.95 V
DRVdd_HP Referenced Ground-centered config 1.5 1.8 1.95
to AVss
(1)
Unipolar config 1.5 3.6
PLL Input Frequency Clock divider uses fractional divide 10 20 MHz
(D > 0), P = 1, DV
dd
≥ 1.65V (See table in SLAU306,
Maximum TLV320AIC3256 Clock Frequencies)
Clock divider uses integer divide 0.512 20 MHz
(D = 0), P = 1, DV
dd
≥ 1.65V (See table in SLAU306,
Maximum TLV320AIC3256 Clock Frequencies)
MCLK Master Clock Frequency MCLK; Master Clock Frequency; DV
dd
≥ 1.65V 50 MHz
MCLK; Master Clock Frequency; DV
dd
≥ 1.26V 25
SCL SCL Clock Frequency 400 kHz
LOL, LOR Stereo line output load resistance 0.6 10 kΩ
HPL, HPR Stereo headphone output load Single-ended configuration 14.4 16 Ω
resistance
Headphone output load resistance Differential configuration 24.4 32 Ω
C
Lout
Digital output load capacitance 10 pF
TOPR Operating Temperature Range –40 85 °C
(1) All grounds on board are tied together; they must not differ in voltage by more than 0.2V max, for any combination of ground signals.
(2) At DVdd values lower than 1.65V, the PLL does not function. Please see table in SLAU306, Maximum TLV320AIC3256 Clock
Frequencies for details on maximum clock frequencies.
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