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TLV320AIC3256

SLOS630B –DECEMBER 2010–REVISED JANUARY 2013

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SPI Control

In the SPI control mode, the TLV320AIC3256 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,

SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit

CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the

master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the

synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the

TLV320AIC3256) depend on a master to start and synchronize transmissions. A transmission begins when

initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the

control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on

the MISO pin to the master shift register.

For more detailed information see the TLV320AIC3256 Application Reference Guide, SLAU306.

Power Supply

The device has an integrated charge pump. In ground-centered headphone configuration, all supplies can be

conveniently supplied from a single 1.5V to 1.95V rail. The device has separate power domains for digital IO,

digital core, analog core, charge-pump input and headphone drive, all of which can be connected together and

be supplied from one source. For improved power efficiency, the digital core voltage can range from 1.26V to

1.95V. The IO voltage can be supplied in the range of 1.1V to 3.6V.

The device power supply Vsys can be supplied in the range of 1.5V to 5.5V. Vsys must always be greater than

or equal to AVdd and DVdd voltages.

For more detailed information see the TLV320AIC3256 Application Reference Guide, SLAU306.

Device Special Functions

The following special functions are available to support advanced system requirements:

• Headset detection

• Interrupt generation

• Flexible pin multiplexing

For more detailed information see the TLV320AIC3256 Application Reference Guide, SLAU306.

Table 11. Summary of Register Map

Decimal Hex DESCRIPTION

PAGE NO. REG. NO. PAGE NO. REG. NO.

0 0 0x00 0x00 Page Select Register

0 1 0x00 0x01 Software Reset Register

0 2 0x00 0x02 Reserved Register

0 3 0x00 0x03 Reserved Register

0 4 0x00 0x04 Clock Setting Register 1, Multiplexers

0 5 0x00 0x05 Clock Setting Register 2, PLL P and R Values

0 6 0x00 0x06 Clock Setting Register 3, PLL J Values

0 7 0x00 0x07 Clock Setting Register 4, PLL D Values (MSB)

0 8 0x00 0x08 Clock Setting Register 5, PLL D Values (LSB)

0 9-10 0x00 0x09-0x0A Reserved Register

0 11 0x00 0x0B Clock Setting Register 6, NDAC Values

0 12 0x00 0x0C Clock Setting Register 7, MDAC Values

0 13 0x00 0x0D DAC OSR Setting Register 1, MSB Value

0 14 0x00 0x0E DAC OSR Setting Register 2, LSB Value

0 15 0x00 0x0F miniDSP_D Instruction Control Register 1

0 16 0x00 0x10 miniDSP_D Instruction Control Register 2

0 17 0x00 0x11 miniDSP_D Interpolation Factor Setting Register

Product Folder Links: TLV320AIC3256