Datasheet

HPL
HPR
GND_SENSE
TLV320AIC3256
SLOS630B DECEMBER 2010REVISED JANUARY 2013
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Analog Audio I/O
The analog IO path of the TLV320AIC3256 features a large set of options for signal conditioning as well as signal
routing:
6 analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
2 mixer amplifiers for analog bypass
2 low power analog bypass channels
Mute function
Channel-to-channel phase adjustment
Fast charge of ac-coupling capacitors
Anti thump
Analog Bypass
The TLV320AIC3256 offers two analog-bypass modes. In either of the modes, an analog input signal can be
routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC
resources are required for such operation.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1_L to the
left headphone amplifier (HPL) and IN1_R to HPR.
ADC Bypass Using Mixer Amplifiers
In addition to the analog low-power bypass mode, another bypass mode uses the programmable gain amplifiers
of the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified
and routed to the line or headphone outputs, fully bypassing the ADC and DAC.
To enable this mode, the mixer amplifiers are powered on via software command.
Headphone Output
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in single-
ended DC-coupled headphone configurations. An integral charge pump generates the negative supply required
to operate the headphone drivers in dc-coupled mode, where the common mode of the output signal is made
equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers in dc-
coupled (ground centered mode) eliminates the need for large dc-blocking capacitors.
Figure 22. TLV320AIC3256 Ground-Centered Headphone Output
Alternatively the headphone amplifier can also be operated in a unipolar circuit configuration using DC blocking
capacitors.
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