Datasheet
TLV320AIC3256
www.ti.com
SLOS630B –DECEMBER 2010–REVISED JANUARY 2013
Electrical Characteristics, Misc.
At 25°C, Vsys, AVdd, DVdd, IOVdd, DVdd_CP, DRVdd_HP = 1.8V, f
S
(Audio) = 48kHz, C
REF
= 1µF on REF PIN, PLL and
Charge pump disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
CMMode = 0 (0.9V) 0.9
Reference Voltage Settings V
CMMode = 1 (0.75V) 0.75
Reference Noise CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, 1.1 μV
RMS
C
REF
= 1μF
Decoupling Capacitor 1 μF
Bias Current 120 μA
miniDSP
(1)
Maximum miniDSP clock frequency - ADC DVdd = 1.65V 58.9 MHz
Maximum miniDSP clock frequency - DAC DVdd = 1.65V 58.9 MHz
Shutdown Current
DVdd is provided externally, no clocks supplied, no
Device Setup
digital activity, register values are retained
I(total) Sum of all supply currents, all supplies at 1.8V <10 μA
(1) The miniDSP clock speed is specified by design and not tested in production.
Electrical Characteristics, Logic Levels
At 25°C, AV
DD
, DV
DD
, IOV
DD
= 1.8V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC FAMILY CMOS
V
IH
Logic Level I
IH
= 5 μA, IOV
DD
> 1.6V 0.7 × IOV
DD
V
I
IH
= 5μA, 1.2V ≤ IOV
DD
< 1.6V 0.9 × IOV
DD
V
I
IH
= 5μA, IOV
DD
< 1.2V IOV
DD
V
V
IL
I
IL
= 5 μA, IOV
DD
> 1.6V –0.3 0.3 × IOV
DD
V
I
IL
= 5μA, 1.2V ≤ IOV
DD
< 1.6V 0.1 × IOV
DD
V
I
IL
= 5μA, IOV
DD
< 1.2V 0 V
V
OH
I
OH
= 2 TTL loads 0.8 × IOV
DD
V
V
OL
I
OL
= 2 TTL loads 0.1 × IOV
DD
V
Capacitive Load 10 pF
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