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TLV320AIC3254

SLAS549C –SEPTEMBER 2008–REVISED OCTOBER 2013

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The audio bus of the TLV320AIC3254 can be configured for left or right-justified, I

S, DSP, or TDM modes of

operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.

These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0,

Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the

beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this

clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,

this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,

lengths, and to support the case when multiple TLV320AIC3254s may share the same audio bus.

The TLV320AIC3254 also includes a feature to offset the position of start of data transfer with respect to the

word-clock. Control the offset in terms of number of bit-clocks by programming Page 0, Register 28.

The TLV320AIC3254 also has the feature to invert the polarity of the bit-clock used to transfer the audio data as

compared to the default clock polarity used. This feature can be used independently of the mode of audio

interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.

The TLV320AIC3254 further includes programmability (Page 0, Register 27, D(0)) to place the DOUT line into a

hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with

the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be

accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data

bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z

output condition.

By default when the word-clocks and bit-clocks are generated by the TLV320AIC3254, these clocks are active

only when the codec (ADC, DAC or both) are powered up within the device. This intermittent clock operation

reduces power consumption. However, it also supports a feature when both the word clocks and bit-clocks can

be active even when the codec in the device is powered down. This continuous clock feature is useful when

using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the

system as general-purpose clocks.

Clock Generation and PLL

The TLV320AIC3254 supports a wide range of options for generating clocks for the ADC and DAC sections as

well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This

clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then

be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the

miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference

clocks on MCLK BCLK or GPIO, the TLV320AIC3254 also provides the option of using the on-chip PLL which

supports a wide range of fractional multiplication values to generate the required clocks. Starting from

CODEC_CLKIN the TLV320AIC3254 provides several programmable clock dividers to help achieve a variety of

sampling rates for ADC, DAC and clocks for the miniDSP.

To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of

the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required

internal clock signals at very low power consumption. For cases where such master clocks are not available, the

built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master

clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible

enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL

is used to generate some other clock that is only used outside the TLV320AIC3254.

For more detailed information see the TLV320AIC3254 Application Reference Guide, SLAA408.

Control Interfaces

The TLV320AIC3254 control interface supports SPI or I

C communication protocols, with the protocol selectable

using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I

C, SPI_SELECT should be tied low.

Changing the state of SPI_SELECT during device operation is not recommended.

Product Folder Links: TLV320AIC3254