Datasheet
TLV320AIC3254
www.ti.com
SLAS549C –SEPTEMBER 2008–REVISED OCTOBER 2013
Table 10. Overview – DAC Predefined Processing Blocks
Processing Interpolation Channel 1st Order Num. of DRC 3D Beep Resource
Block No. Filter IIR Available Biquads Generator Class
PRB_P1
(1)
A Stereo No 3 No No No 8
PRB_P2 A Stereo Yes 6 Yes No No 12
PRB_P3 A Stereo Yes 6 No No No 10
PRB_P4 A Left No 3 No No No 4
PRB_P5 A Left Yes 6 Yes No No 6
PRB_P6 A Left Yes 6 No No No 6
PRB_P7 B Stereo Yes 0 No No No 6
PRB_P8 B Stereo No 4 Yes No No 8
PRB_P9 B Stereo No 4 No No No 8
PRB_P10 B Stereo Yes 6 Yes No No 10
PRB_P11 B Stereo Yes 6 No No No 8
PRB_P12 B Left Yes 0 No No No 3
PRB_P13 B Left No 4 Yes No No 4
PRB_P14 B Left No 4 No No No 4
PRB_P15 B Left Yes 6 Yes No No 6
PRB_P16 B Left Yes 6 No No No 4
PRB_P17 C Stereo Yes 0 No No No 3
PRB_P18 C Stereo Yes 4 Yes No No 6
PRB_P19 C Stereo Yes 4 No No No 4
PRB_P20 C Left Yes 0 No No No 2
PRB_P21 C Left Yes 4 Yes No No 3
PRB_P22 C Left Yes 4 No No No 2
PRB_P23 A Stereo No 2 No Yes No 8
PRB_P24 A Stereo Yes 5 Yes Yes No 12
PRB_P25 A Stereo Yes 5 Yes Yes Yes 12
(1) Default
For more detailed information see the TLV320AIC3254 Application Reference Guide, SLAA408.
Powertune
The TLV320AIC3254 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance,
or to an operating point between the two extremes to best fit the application. The TLV320AIC3254 PowerTune
modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback
(DAC) path.
For more detailed information see the TLV320AIC3254 Application Reference Guide, SLAA408.
Digital Audio IO Interface
Audio data flows between the host processor and the TLV320AIC3254 on the digital audio data serial interface,
or audio bus. This very flexible bus includes left or right-justified data options, support for I
2
S or PCM protocols,
programmable data length options, a TDM mode for multichannel operation, very flexible master-slave
configurability for each bus clock line, and the ability to communicate with multiple devices within a system
directly.
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