Datasheet

TLV320AIC3254
www.ti.com SLAS549C –SEPTEMBER 2008–REVISED OCTOBER 2013
I
2
C Control
The TLV320AIC3254 supports the I
2
C control protocol, and will respond to the I
2
C address of 0011000. I
2
C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I
2
C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This circuit prevents two devices from conflicting; if two devices drive the bus simultaneously, there is no driver
contention.
SPI Control
In the SPI control mode, the TLV320AIC3254 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3254) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the TLV320AIC3254 Application Reference Guide, SLAA408.
Power Supply
To power up the device, a 3.3V system rail (1.9V to 3.6V) can be used. The IO
VDD
voltage can be in the range of
1.1V - 3.6V. Internal LDOs can generate the appropriate digital and analog core voltages when configured to do
so. For maximum flexibility, the respective voltages can also be supplied externally, bypassing the built-in LDOs.
To support high-output drive capabilities, the output stages of the output amplifiers can be driven from the analog
core voltage or the 1.9…3.6V rail used for the LDO inputs (LDO_in).
For more detailed information see the TLV320AIC3254 Application Reference Guide, SLAA408.
Device Special Functions
The following special functions are available to support advanced system requirements:
• Headset detection
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the TLV320AIC3254 Application Reference Guide, SLAA408.
The TLV320AIC3254 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the
second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP must be
loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the
ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each
miniDSP can run up to 1152 instructions on every audio sample at a 48kHz sample rate. The two cores can run
fully synchronized and can exchange data.
Software
Software development for the TLV320AIC3254 is supported through TI's comprehensive PurePath Studio
Development Environment; a powerful, easy-to-use tool designed specifically to simplify software development
on the TLV320AIC3254 miniDSP audio platform. The Graphical Development Environment consists of a library of
common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected
together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse.
Please visit the TLV320AIC3254 product folder on www.ti.com to learn more about PurePath Studio and the
latest status on available, ready-to-use DSP algorithms.
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Product Folder Links: TLV320AIC3254