Datasheet
TLV320AIC3204
SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012
www.ti.com
Electrical Characteristics
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
AV
DD
to AV
SS
–0.3 to 2.2 V
DV
DD
to DV
SS
–0.3 to 2.2 V
IOV
DD
to IOV
SS
–0.3 to 3.9 V
LDOIN to AV
SS
–0.3 to 3.9 V
Digital Input voltage to ground –0.3 to IOV
DD
+ 0.3 V
Analog input voltage to ground –0.3 to AV
DD
+ 0.3 V
Operating temperature range –40 to 85 °C
Storage temperature range –55 to 125 °C
Junction temperature (T
J
Max) 105 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN NOM MAX UNIT
LDOIN Power Supply Voltage Range Referenced to AV
SS
(1)
1.9 3.6 V
AV
DD
1.5 1.8 1.95
IOV
DD
Referenced to IOV
SS
(1)
1.1 3.6
DV
DD
(2)
Referenced to DV
SS
(1)
1.26 1.8 1.95
PLL Input Frequency Clock divider uses fractional divide 10 20 MHz
(D > 0), P = 1, DV
DD
≥ 1.65V (See table in SLAA557,
Maximum TLV320AIC3204 Clock Frequencies)
Clock divider uses integer divide 0.512 20 MHz
(D = 0), P = 1, DV
DD
≥ 1.65V (See table in SLAA557,
Maximum TLV320AIC3204 Clock Frequencies)
MCLK Master Clock Frequency MCLK; Master Clock Frequency; DV
DD
≥ 1.65V 50 MHz
MCLK; Master Clock Frequency; DV
DD
≥ 1.26V 25
SCL SCL Clock Frequency 400 kHz
LOL, Stereo line output load resistance 0.6 10 kΩ
LOR
HPL, Stereo headphone output load Single-ended configuration 14.4 16 Ω
HPR resistance
Headphone output load resistance Differential configuration 24.4 32 Ω
C
Lout
Digital output load capacitance 10 pF
TOPR Operating Temperature Range –40 85 °C
(1) All grounds on board are tied together to prevent voltage differences of more than 0.2V maximum for any combination of ground signals.
(2) At DV
DD
values lower than 1.65V, the PLL does not function. Please see the Maximum TLV320AIC3204 Clock Frequencies table in the
TLV320AIC3204 Application Reference Guide (SLAA557) for details on maximum clock frequencies.
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