Datasheet

TLV320AIC3204
www.ti.com SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012
SPI Control
In the SPI control mode, the TLV320AIC3204 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320AIC3204) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the TLV320AIC3204Application Reference Guide, SLAA557.
Power Supply
To power up the device, a 3.3V system rail (1.9V to 3.6V) can be used. The IO
VDD
voltage can be in the range of
1.1V - 3.6V. Internal LDOs generate the appropriate digital core voltage of 1.65V and analog core voltage of 1.8V
(minimum 1.5V). For maximum flexibility, the respective voltages can also be supplied externally, bypassing the
built-in LDOs. To support high-output drive capabilities, the output stages of the output amplifiers can be driven
from the analog core voltage or the 1.9…3.6V rail used for the LDO inputs (LDO_in).
For more detailed information see the TLV320AIC3204Application Reference Guide, SLAA557.
Device Special Functions
The following special functions are available to support advanced system requirements:
• Headset detection
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the TLV320AIC3204Application Reference Guide, SLAA557.
Register Map Summary
Table 11. Summary of Register Map
Decimal Hex DESCRIPTION
PAGE NO. REG. NO. PAGE NO. REG. NO.
0 0 0x00 0x00 Page Select Register
0 1 0x00 0x01 Software Reset Register
0 2 0x00 0x02 Reserved Register
0 3 0x00 0x03 Reserved Register
0 4 0x00 0x04 Clock Setting Register 1, Multiplexers
0 5 0x00 0x05 Clock Setting Register 2, PLL P&R Values
0 6 0x00 0x06 Clock Setting Register 3, PLL J Values
0 7 0x00 0x07 Clock Setting Register 4, PLL D Values (MSB)
0 8 0x00 0x08 Clock Setting Register 5, PLL D Values (LSB)
0 9-10 0x00 0x09-0x0A Reserved Register
0 11 0x00 0x0B Clock Setting Register 6, NDAC Values
0 12 0x00 0x0C Clock Setting Register 7, MDAC Values
0 13 0x00 0x0D DAC OSR Setting Register 1, MSB Value
0 14 0x00 0x0E DAC OSR Setting Register 2, LSB Value
0 15 0x00 0x0F Reserved Register
0 16 0x00 0x10 Reserved Register
0 17 0x00 0x11 Reserved Register
0 18 0x00 0x12 Clock Setting Register 8, NADC Values
0 19 0x00 0x13 Clock Setting Register 9, MADC Values
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