Datasheet
TLV320AIC3204
SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012
www.ti.com
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word
lengths, and to support the case when multiple TLV320AIC3204s may share the same audio bus.
The TLV320AIC3204 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. Control the offset in terms of number of bit-clocks by programming Page 0, Register 28.
The TLV320AIC3204 also has the feature to invert the polarity of the bit-clock used to transfer the audio data as
compared to the default clock polarity used. This feature can be used independently of the mode of audio
interface chosen. Page 0, Register 29, D(3) configures bit clock polarity.
The TLV320AIC3204 further includes programmability (Page 0, Register 27, D(0)) to place the DOUT line into a
hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with
the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3204, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This intermittent clock operation
reduces power consumption. However, it also supports a feature when both the word clocks and bit-clocks can
be active even when the codec in the device is powered down. This continuous clock feature is useful when
using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the
system as general-purpose clocks.
Clock Generation and PLL
The TLV320AIC3204 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for the ADC and DAC
sections. In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK,
BCLK or GPIO, the TLV320AIC3204 also provides the option of using the on-chip PLL which supports a wide
range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the
TLV320AIC3204 provides several programmable clock dividers to help achieve a variety of sampling rates for
ADC, DAC and clocks for the processing block.
To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of
the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required
internal clock signals at very low power consumption. For cases where such master clocks are not available, the
built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master
clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible
enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL
is used to generate some other clock that is only used outside the TLV320AIC3204.
For more detailed information see the TLV320AIC3204Application Reference Guide, SLAA557.
Control Interfaces
The TLV320AIC3204 control interface supports SPI or I
2
C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I
2
C, SPI_SELECT should be tied low.
Changing the state of SPI_SELECT during device operation is not recommended.
I
2
C Control
The TLV320AIC3204 supports the I
2
C control protocol, and will respond to the I
2
C address of 0011000. I
2
C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I
2
C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This circuit prevents two devices from conflicting; if two devices drive the bus simultaneously, there is no driver
contention.
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