Datasheet

IN1_L
IN1_R
HPLHPR
LOL
LOR
LDOIN
DVDD
IOVDD
1.9...3.6V
MICBIAS
AVDD
LDO_SELECT
10 uF
0.1uF
1.0uF 10uF
IN2_L
IN2_R
MFP3/SCLK
IN3_R
AVSS DVSS IOVSS
1.1...3.6V
REF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
2.7k1k1k
1k
47uF
1k
4700pF
0.1uF
1k
4700pF
0.1uF
0.1uF
0.1uF
TPA2012
Class D Amp
10 uF 10 uF
1k
47uF
Reset DINWCLKSCL SDA BCLK
DOUT
SPI_Select
MCLK
Headset_Mic
Headset_Spkr_R
Headset_Spkr_L
Headset_Gnd
Earjack
microphone
and headset
speakers
Host Processor
TLV320AIC3204
www.ti.com SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012
TYPICAL CIRCUIT CONFIGURATION
Figure 21. Typical Circuit Configuration
Application Overview
The TLV320AIC3204 offers a wide range of configuration options. Figure 1 shows the basic functional blocks of
the device.
Device Connections
Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are Reset, LDO_Select and the SPI_Select pin, which are HW control pins. Depending on
the state of SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I
2
C or SPI
protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Multifunction Pins.
Multifunction Pins
Table 8 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Copyright © 2008–2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TLV320AIC3204