Datasheet

t
td
S
t
a
MSB OUT BIT 6 . . . 1 LSB OUT
t
sck
t
Lead
t
Lag
t
sckh
t
sckl
t
r
t
f
t
v(DOUT)
t
dis
MSB IN BIT 6 . . . 1 LSB IN
t
hi
t
su
SS
SCLK
MISO
MOSI
TLV320AIC3204
www.ti.com SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012
SPI Interface Timing
Figure 8. SPI Interface Timing Diagram
Timing Requirements
At 25°C, DVdd = 1.8V
Table 7. SPI Interface Timing (See Figure 8)
PARAMETER TEST CONDITION IOVDD=1.8V IOVDD=3.3V UNITS
MIN TYP MAX MIN TYP MAX
t
sck
SCLK Period
(1)
100 50 ns
t
sckh
SCLK Pulse width High 50 25 ns
t
sckl
SCLK Pulse width Low 50 25 ns
t
lead
Enable Lead Time 30 20 ns
t
trail
Enable Trail Time 30 20 ns
t
d;seqxfr
Sequential Transfer Delay 40 20 ns
t
a
Slave DOUT access time 40 20 ns
t
dis
Slave DOUT disable time 40 20 ns
t
su
DIN data setup time 15 10 ns
t
h;DIN
DIN data hold time 15 10 ns
t
v;DOUT
DOUT data valid time 25 18 ns
t
r
SCLK Rise Time 4 4 ns
t
f
SCLK Fall Time 4 4 ns
(1) These parameters are based on characterization and are not tested in production.
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