Datasheet

TLV320AIC3204
SLOS602B –SEPTEMBER 2008–REVISED OCTOBER 2012 www.ti.com
I
2
C Interface Timing
Figure 7. I
2
C Interface Timing
Table 6. I
2
C Interface Timing
PARAMETER TEST CONDITION Standard-Mode Fast-Mode UNITS
MIN TYP MAX MIN TYP MAX
f
SCL
SCL clock frequency 0 100 0 400 kHz
t
HD;STA
Hold time (repeated) START 4.0 0.8 μs
condition. After this period, the first
clock pulse is generated.
t
LOW
LOW period of the SCL clock 4.7 1.3 μs
t
HIGH
HIGH period of the SCL clock 4.0 0.6 μs
t
SU;STA
Setup time for a repeated START 4.7 0.8 μs
condition
t
HD;DAT
Data hold time: For I2C bus 0 3.45 0 0.9 μs
devices
t
SU;DAT
Data set-up time 250 100 ns
t
r
SDA and SCL Rise Time 1000 20+0.1C
b
300 ns
t
f
SDA and SCL Fall Time 300 20+0.1C
b
300 ns
t
SU;STO
Set-up time for STOP condition 4.0 0.8 μs
t
BUF
Bus free time between a STOP 4.7 1.3 μs
and START condition
C
b
Capacitive load for each bus line 400 400 pF
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