Datasheet

TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
Page 0 / Register 83: Reserved Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D0 R/W 0000000 Reserved. Write only '0000000' to this register.
Page 0 / Register 84: PGA_R to LEFT_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to LEFT_LOP/M
1: PGA_R is routed to LEFT_LOP/M
D6-D0 R/W 0000000 PGA_R to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5 .
Page 0 / Register 85: DAC_R1 to LEFT_LOP/M Volume Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to LEFT_LOP/M
1: DAC_R1 is routed to LEFT_LOP/M
D6-D0 R/W 0000000 DAC_R1 to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 5 .
Page 0 / Register 86: LEFT_LOP/M Output Level Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D4 R/W 0000 LEFT_LOP/M Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010 – 1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 LEFT_LOP/M Mute
0: LEFT_LOP/M is muted
1: LEFT_LOP/M is not muted
D2 R/W 0 Reserved. Write only '0' to this register bit.
D1 R 1 LEFT_LOP/M Volume Control Status
0: Not all programmed gains to LEFT_LOP/M have been applied yet
1: All programmed gains to LEFT_LOP/M have been applied
D0 R/W 0 LEFT_LOP/M Power Control
0: LEFT_LOP/M is not fully powered up
1: LEFT_LOP/M is fully powered up
Page 0 / Register 87: Reserved Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D0 R/W 0 Reserved. Write only '0000000' to this register.
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