Datasheet
TLV320AIC31
SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008 .............................................................................................................................................
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Page 0 / Register 20: Reserved Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D0 R/W 0111100 Reserved. Do not write to this register.
0
Page 0 / Register 21: IN1R to Left ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 IN1R Single-Ended vs Fully-Differential Control If IN1R is selected to both left and right ADC
channels, both connections must use the same configuration (single-ended or fully-differential
mode).
0: IN1R is configured in single-ended mode
1: IN1R is configured in fully-differential mode
D6 – D3 R/W 1111 IN1R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects IN1R to the left ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = – 1.5-dB
0010: Input level control gain = – 3.0-dB
0011: Input level control gain = – 4.5-dB
0100: Input level control gain = – 6.0-dB
0101: Input level control gain = – 7.5-dB
0110: Input level control gain = – 9.0-dB
0111: Input level control gain = – 10.5-dB
1000: Input level control gain = – 12.0-dB
1001 – 1110: Reserved. Do not write these sequences to these register bits
1111: IN1R is not connected to the left ADC PGA
D2 – D0 R 000 Reserved. Write only 0s to these register bits.
Page 0 / Register 22: IN1R to Right ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 IN1R Single-Ended vs Fully-Differential Control If IN1R is selected to both left and right ADC
channels, both connections must use the same configuration (single-ended or fully-differential
mode).
0: IN1R is configured in single-ended mode
1: IN1R is configured in fully-differential mode
D6 – D3 R/W 1111 IN1R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects IN1R to the right ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = – 1.5-dB
0010: Input level control gain = – 3.0-dB
0011: Input level control gain = – 4.5-dB
0100: Input level control gain = – 6.0-dB
0101: Input level control gain = – 7.5-dB
0110: Input level control gain = – 9.0-dB
0111: Input level control gain = – 10.5-dB
1000: Input level control gain = – 12.0-dB
1001 – 1110: Reserved. Do not write these sequences to these register bits
1111: IN1R is not connected to the right ADC PGA
D2 R/W 0 Right ADC Channel Power Control
0: Right ADC channel is powered down
1: Right ADC channel is powered up
D1 – D0 R/W 00 Right ADC PGA Soft-Stepping Control
00: Right ADC PGA soft-stepping at once per F
S
01: Right ADC PGA soft-stepping at once per two F
S
10-11: Right ADC PGA soft-stepping is disabled
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