Datasheet

RIGHT-JUSTIFIED MODE
BCLK
WCLK
SDIN/
SDOUT
1 00 1 0
1/fs
LSBMSB
LeftChannel RightChannel
2 2
n−1
n−3
n−2
n−1
n−3
n−2
LEFT-JUSTIFIED MODE
n-1 n-2 n-3 n-1 n-2 n-3
I
2
S MODE
n-1 n-2 n-3 n-1 n-2 n-3
TLV320AIC31
www.ti.com ............................................................................................................................................. SLAS497C – AUGUST 2006 – REVISED DECEMBER 2008
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 18. Right-Justified Serial Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
Figure 19. Left-Justified Serial Data Bus Mode Operation
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
Figure 20. I
2
S Serial Data Bus Mode Operation
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