Datasheet
TLV320AIC3120
SLAS653A –FEBRUARY 2010–REVISED MAY 2012
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Page 0 / Register 61 (0x3D): ADC Processing Block / miniDSP Selection
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D5 R/W 000 Reserved. Write only default values.
D4–D0 R/W 0 0100 0 0000: ADC miniDSP is used for signal processing.
0 0001–0 0011: Reserved. Do not use.
0 0100: ADC signal-processing block PRB_R4
0 0101: ADC signal-processing block PRB_R5
0 0110: ADC signal-processing block PRB_R6
0 0111–01001: Reserved. Do not use.
0 1010: ADC signal-processing block PRB_R10
0 1011: ADC signal-processing block PRB_R11
0 1100: ADC signal-processing block PRB_R12
0 1101–0 1111: Reserved. Do not use.
1 0000: ADC signal-processing block PRB_R16
1 0001: ADC signal-processing block PRB_R17
1 0010: ADC signal-processing block PRB_R18
1 0011–1 1111: Reserved. Do not write these sequences to these bits.
Page 0 / Register 62 (0x3E): Programmable miniDSP Instruction Mode-Control Bits
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved
D6 R/W 0 ADC miniDSP Engine Auxilliary Control bit A, Which Can Be Used for Conditional Instructions Like JMP
D5 R/W 0 ADC miniDSP Engine Auxilliary Control bit B, Which Can Be Used for Conditional Instructions Like JMP
D4 R/W 0 0: Reset ADC miniDSP instruction counter at the start of the new frame.
1: Do not reset ADC miniDSP instruction counter at the start of the new frame.
D3 R/W 0 Reserved
D2 R/W 0 DAC miniDSP Engine Auxilliary Control bit A, Which Can Be Used for Conditional Instructions Like JMP
D1 R/W 0 DAC miniDSP Engine Auxilliary Control bit B, Which Can Be Used for Conditional Instructions Like JMP
D0 R/W 0 0: Reset DAC miniDSP instruction counter at the start of the new frame.
1: Do not reset DAC miniDSP instruction counter at the start of the new frame.
Page 0 / Register 63 (0x3F): DAC Data-Path Setup
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: DAC is powered down.
1: DAC is powered up.
D6 R/W 0 Reserved. Write only 0 to this bit.
D5–D4 R/W 01 00: DAC data path = off
01: DAC data path = left data
10: DAC data path = right data
11: DAC data path = left and right data [(L + R)/2]
D3–D2 R/W 01 Reserved
D1–D0 R/W 00 00: DAC channel volume-control soft-stepping is enabled for one step per sample period.
01: DAC channel volume-control soft-stepping is enabled for one step per two sample periods.
10: DAC channel volume-control soft-stepping is disabled.
11: Reserved. Do not write this sequence to these bits.
Page 0 / Register 64 (0x40): DAC VOLUME CONTROL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 Reserved. Write only zeros to these bits.
D3 R/W 1 0: DAC not muted
1: DAC muted
D2–D0 R/W 100 Reserved. Always write reset value.
94 REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated
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