Datasheet

Start
(M)
7-bitDevice Address
(M)
Write
(M)
Slave
Ack
(S)
8-bitRegister Address
(M)
Slave
Ack
(S)
SDA
SCL
7-bitDevice Address
(M)
Read
(M)
Slave
Ack
(S)
DA(6) DA(0) RA(7) RA(0)
DA(6) DA(0) D(7) D(0)
8-bitRegisterData
(S)
Stop
(M)
Master
No Ack
(M)
Repeat
Start
(M)
(M)=>SDA ControlledbyMaster
(S)=>SDA ControlledbySlave
DA(6) DA(0) RA(7) RA(0) D(7) D(0)
Start
(M)
7-bitDevice Address
(M)
Write
(M)
Slave
Ack
(S)
8-bitRegister Address
(M)
Slave
Ack
(S)
8-bitRegisterData
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M)=>SDA ControlledbyMaster
(S)=>SDA ControlledbySlave
TLV320AIC3120
www.ti.com SLAS653A –FEBRUARY 2010–REVISED MAY 2012
Figure 5-50. I
2
C Write
Figure 5-51. I
2
C Read
In the case of an I
2
C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next
incremental register.
Similarly, in the case of an I
2
C register read, after the device has sent out the 8-bit data from the
addressed register, if the master issues an ACKNOWLEDGE, the slave takes over control of the SDA bus
and transmits for the next eight clocks the data of the next incremental register.
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 81
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