Datasheet

PLL _ CLKIN
10 MHz 20 MHz
P
£ £
TLV320AIC3120
www.ti.com SLAS653A –FEBRUARY 2010–REVISED MAY 2012
4 ≤ R × J ≤ 259
• When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN:
(11)
80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz
R = 1
The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a
general-purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is
available typically after 10 ms.
The clock for the codec and various signal processing blocks, CODEC_CLKIN, can be generated from the
MCLK input, BCLK input, GPIO input, or PLL_CLK (page 0 / register 4, bits D1–D0).
If the CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down
last.
Table 5-37 lists several example cases of typical PLL_CLKIN rates and how to program the PLL to
achieve a sample rate f
S
of either 44.1 kHz or 48 kHz.
Table 5-37. PLL Example Configurations
PLL_CLKIN
PLLP PLLR PLLJ PLLD MADC NADC AOSR MDAC NDAC DOSR
(MHz)
f
S
= 44.1 kHz
2.8224 1 3 10 0 3 5 128 3 5 128
5.6448 1 3 5 0 3 5 128 3 5 128
12 1 1 7 560 3 5 128 3 5 128
13 1 1 6 3504 2 9 104 6 3 104
16 1 1 5 2920 3 5 128 3 5 128
19.2 1 1 4 4100 3 5 128 3 5 128
48 4 1 7 560 3 5 128 3 5 128
f
S
= 48 kHz
2.048 1 3 14 0 2 7 128 7 2 128
3.072 1 4 7 0 2 7 128 7 2 128
4.096 1 3 7 0 2 7 128 7 2 128
6.144 1 2 7 0 2 7 128 7 2 128
8.192 1 4 3 0 2 8 128 4 4 128
12 1 1 7 1680 2 7 128 7 2 128
16 1 1 5 3760 2 7 128 7 2 128
19.2 1 1 4 4800 2 7 128 7 2 128
48 4 1 7 1680 2 7 128 7 2 128
5.7.2 Timer
The internal clock runs nominally at 8.2 MHz. This is used for various internal timing intervals, de-bounce
logic, and interrupts. The MCLK divider must be set in such a way that the divider output is approximately
1 MHz for the timers to be closer to the programmed value.
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 71
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