Datasheet
÷M
CLKOUT
CDIV_CLKIN
MCLK BCLK DIN
PLL_CLK
DAC_CLK ADC_CLK
DAC_MOD_CLK ADC_MOD_CLK
M=1,2,...,127,128
GPIO1
DOUT
÷ N
BCLK
DAC_CLK
ADC_MOD_CLK
DAC_MOD_CLK
ADC_CLK
BDIV_CLKIN
N = 1, 2, ..., 127, 128
TLV320AIC3120
www.ti.com
SLAS653A –FEBRUARY 2010–REVISED MAY 2012
Figure 5-35. ¿
In the mode when the TLV320AIC3120 is configured to drive the BCLK pin (page 0 / register 27,
bit D3 = 1), it can be driven as a divided value of BDIV_CLKIN. The division value can be programmed in
page 0 / register 30, bits D6–D0 from 1 to 128. The BDIV_CLKIN can itself be configured to be one of
DAC_CLK (DAC DSP clock), DAC_MOD_CLK, ADC_CLK (ADC DSP clock), or ADC_MOD_CLK by
configuring the BDIV_CLKIN multiplexer in page 0 / register 29, bits D1–D0. Additionally, a general-
purpose clock can be driven out on either GPIO1 or DOUT.
This clock can be a divided down version of CDIV_CLKIN. The value of this clock divider can be
programmed from 1 to 128 by writing to page 0 / register 26, bits D6–D0. The CDIV_CLKIN can itself be
programmed as one of the clocks among the list shown in Figure 5-36. This can be controlled by
programming the multiplexer in page 0 / register 25, bits D2–D0.
Figure 5-36. General-Purpose Clock Output Options
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 69
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