Datasheet

PLL
´ ´(R J.D)/P
PLL_CLKIN
CODEC_CLKIN
ADC_CLK
DAC_MOD_CLK
DAC_CLK
ADC_MOD_CLK
NDAC = 1, 2, ..., 127, 128
MDAC = 1, 2, ..., 127, 128
DOSR = 1, 2, ..., 1023, 1024 AOSR = 1, 2, ..., 255, 266
MADC = 1, 2, ..., 127, 128
NADC = 1, 2, ..., 127, 128
MCLK
BCLK
GPIO1
DIN
MCLK
BCLK
GPIO1
PLL_CLK
¸ NADC
¸ MADC¸ MDAC
¸ DOSR ¸ AOSR
¸ NDAC
To DAC_miniDSP
Clock Generation
To ADC_miniDSP
Clock Generation
DAC_f
S
ADC_f
S
B0357-02
TLV320AIC3120
www.ti.com SLAS653A –FEBRUARY 2010–REVISED MAY 2012
5.7 CLOCK Generation and PLL
The TLV320AIC3120 supports a wide range of options for generating clocks for the ADC and DAC
sections as well as the interface and other control blocks shown in Figure 5-34. The clocks for ADC and
DAC require a source reference clock. This clock can be provided on variety of device pins, such as
MCLK, BCLK, or GPIO1 pins. The source reference clock for the codec can be chosen by programming
the CODEC_CLKIN value on page 0 / register 4, bits D1–D0. CODEC_CLKIN can then be routed through
highly-flexible clock dividers shown in Figure 5-34 to generate the various clocks required for ADC, DAC
and digital processing sections. In the event that the desired audio or miniDSP clocks cannot be
generated from the reference clocks on MCLK, BCLK, or GPIO1, the TLV320AIC3120 also provides the
option of using the on-chip PLL, which supports a wide range of fractional multiplication values to generate
the required clocks. Starting from CODEC_CLKIN, the TLV320AIC3120 provides several programmable
clock dividers to help achieve a variety of sampling rates for the ADC and DAC.
Figure 5-34. Clock Distribution Tree
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 67
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