Datasheet

TLV320AIC3120
SLAS653A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
# 3. Program Analog Blocks
# (a) Set register Page to 1
#
w 30 00 01
#
# (b) Program MICBIAS if applicable
#
# Programmed MICBIAS always on, 2.5V
# w 30 2E 0A
# Micbias = AVDD
w 30 2e 0a
#
# (c) Program MicPGA
# (d) Routing of inputs/common mode to ADC input
# (e) Unmute analog PGAs and set analog gain
#
# MICPGA P = MIC1LP 20kohm
w 30 30 80
#
# MICPGA M - CM 20kohm
w 30 31 80
#
# 4. Program ADC
#
# (a) Set register Page to 0
#
w 30 00 00
#
# (b) Power up ADC channel
w 30 51 80
#
# (c) Unmute digital volume control and set gain
#
# UNMUTE
w 30 52 00
#
5.6 Audio DAC and Audio Analog Outputs
The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital
delta-sigma modulator, and an analog reconstruction filter. The DAC high oversampling ratio (normally
DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise
generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog
outputs include mono headphone/lineout and mono class-D speaker outputs. Because the
TLV320AIC3102 has only a mono DAC, it inputs the mono data from the left channel, the right channel, or
a mix of the left and right channels as [(L + R) ÷ 2], controlled by setting page 0 / register 63, bits D5–D4.
See Figure 1-1 for the signal flow.
5.6.1 DAC
The TLV320AIC3120 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of
the mono DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction
filter. The DAC is designed to provide enhanced performance at low sampling rates through increased
oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma
modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. To handle
multiple input rates and optimize power dissipation and performance, the TLV320AIC3120 allows the
system designer to program the oversampling rates over a wide range from 1 to 1024 by configuring
page 0 / register 13 and page 0 / register 14. The system designer can choose higher oversampling ratios
for lower input data rates and lower oversampling ratios for higher input data rates.
The TLV320AIC3120 DAC channel includes a built-in digital interpolation filter to generate oversampled
data for the delta-sigma modulator. The interpolation filter can be chosen from three different types,
depending on required frequency response, group delay, and sampling rate.
42 APPLICATION INFORMATION Copyright © 2010–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLV320AIC3120