Datasheet

TLV320AIC3120
www.ti.com SLAS653A –FEBRUARY 2010–REVISED MAY 2012
Mode B
To choose mode B, page 0 / register 102, bit D5 must be programmed to 1. In dc-measurement mode B,
a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0 / register 102, bits
D4–D0. The nature of the filter is given in Table 5-19.
Table 5-19. DC Measurement Bandwidth Settings
D:Page 0 / Register 102, Bits D4–D0 –3-dB BW (kHz) –0.5-dB BW (kHz)
1 688.44 236.5
2 275.97 96.334
3 127.4 44.579
4 61.505 21.532
5 30.248 10.59
6 15.004 5.253
7 7.472 2.616
8 3.729 1.305
9 1.862 652
10 931 326
11 465 163
12 232.6 81.5
13 116.3 40.7
14 58.1 20.3
15 29.1 10.2
16 14.54 5.09
17 7.25 2.54
18 3.63 1.27
19 1.8 0.635
20 0.908 0.3165
By programming page 0 / register 103, bit D5 to 1, the averaging filter is periodically reset after 2
R
number
of ADC_MOD_CLK periods, where R is programmed in page 0 / register 103, bits D4–D0. When page 0 /
register 103, bit D5 is set to 1, then the value of D should be less than the value of R. When page 0 /
register 103, bit D5 is programmed to 0, the averaging filter is never reset.
5.5.8 ADC Setup
The following paragraphs are intended to guide a user through the steps necessary to configure the
TLV320AIC3120 ADC.
Step 1
The system clock source (master clock) and the targeted ADC sampling frequency must be identified.
Depending on the targeted performance, the decimation filter type (A, B, or C) and AOSR value can be
determined:
• Filter A should be used for 48-kHz high-performance operation; AOSR must be a multiple of 8.
• Filter B should be used for up to 96-kHz operations; AOSR must be a multiple of 4.
• Filter C should be used for up to 192-kHz operations; AOSR must be a multiple of 2.
In all cases, AOSR is limited in its range by the following condition:
2.8 MHz < AOSR × ADC_f
S
< 6.2 MHz
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 39
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