Datasheet
TLV320AIC3120
www.ti.com
SLAS653A –FEBRUARY 2010–REVISED MAY 2012
5.2.2 Audio Analog I/O
The TLV320AIC3120 has a mono audio DAC and a mono ADC. It supports a wide range of analog
interfaces to support different headsets and analog outputs. The TLV320AIC3120 has features to interface
output drivers (8-Ω, 16-Ω, 32-Ω) and a microphone PGA with AGC control.
5.3 miniDSP
The TLV320AIC3120 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC;
the second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the
miniDSP must be loaded into the device after power up. The miniDSPs have direct access to the digital
audio stream on the ADC and on the DAC side, offering the possibility for advanced, very low-group-delay
DSP algorithms.
The ADC miniDSP has 384 programmable instructions, 256 data memory locations, and 128
programmable coefficients. The DAC miniDSP has 1024 programmable instructions, 896 data memory
locations, and 512 programmable coefficients (in the adaptive mode, there are two banks of 256
programmable coefficients each).
5.3.1 Software
Software development for the TLV320AIC3120 is supported through TI's comprehensive PurePath™
Studio software development environment, a powerful, easy-to-use tool designed specifically to simplify
software development on Texas Instruments miniDSP audio platforms. The graphical development
environment consists of a library of common audio functions that can be dragged and dropped into an
audio signal flow and graphically connected together. The DSP code can then be assembled from the
graphical signal flow with the click of a mouse.
See the TLV320AIC3120 product folder on www.ti.com to learn more about PurePath Studio software and
the latest status on available, ready-to-use DSP algorithms.
5.4 Digital Processing Low-Power Modes
The TLV320AIC3120 device can be tuned to minimize power dissipation, to maximize performance, or to
an operating point between the two extremes to best fit the application. The choice of processing blocks,
PRB_P4 to PRB_P22 for mono playback and PRB_R4 to PRB_R18 for mono recording, also influences
the power consumption. In fact, the numerous processing blocks have been implemented to offer a choice
among configurations having a different balance of power-optimization and signal-processing capabilities.
5.4.1 ADC, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V
AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A)
Power consumption = 9.01 mW
Table 5-1. PRB_R4 Alternative Processing Blocks, 9.01 mW
Processing Block Filter Estimated Power Change (mW)
PRB_R5 A 0.23
PRB_R6 A 0.22
Copyright © 2010–2012, Texas Instruments Incorporated APPLICATION INFORMATION 21
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