Datasheet

Audio Output Stage
Power Management
RC CLK
Digital
Audio
Processing
and
Serial
Interface
SDOUT
SDIN
BCLK
WCLK
MCLKPLL
7-Bit ADC P0/R117
Volume-Control Register
P0/R116
Digital Vol
24 dB to
Mute
P0/R64
miniDSP
Processing
Blocks
SPKP
SPKP
SPKM
SPKM
Class-D Speaker
Driver
6 dB to 24 dB (6-dB Steps)
Class A/B
Headphone/Lineout
Driver
0 dB to 9 dB (1-dB Steps)
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
HPVDD
SPKVDD SPKVSS
AVDD
AVSSSPKVSSSPKVDD
VOL/
MICDET
HPOUT
SCL
SDA
GPIO GPIO1
MIX
MIX
MIC1LP
DAC
MIX
RESET
DVDD
DVSS
IOVDD IOVSS
OSC
RC CLK
MIC1LP
Selectable
Gain/Input
Impedance
VCOM
Selectable
Gain/Input
Impedance
P1/R47
0 to 59.5 dB
(0.5-dB steps)
AGC
MIC1RP
I C
2
2 V/2.5 V/AVDD
MICBIAS
Digital Vol
–12..20 dB
Step = 0.5 dB
Mono ADC
Note: Normally,
MCLK is PLL input;
however, BCLK
and GPIO1 can
also be PLL input.
D S-
ADC
D S-
DAC
De-Pop
and
Soft-
Start
P1/R33–R34
S
S
S
P1/R42
P1/R46
P1/R38
P1/R30
P1/R40
P1/R31
P1/R36
P0/R86–R93
P1/R48
P1/R49
Input CM
P1/R50
B0205-06
P0/R82–R83
HPVSS
MIC1RP
MIC1LM
Mono DAC
Digtal Mic
Interface
Clock
Data
Note: Digital Mic
Clock and Data
routed to GPIO1
and DIN pins.
P0/R51 and R54
L Data
L Data
R Data
(L + R)/2 Data
P0/R63
miniDSP
Processing
Blocks
TLV320AIC3120
SLAS653A FEBRUARY 2010REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Figure 1-1. Functional Block Diagram
NOTE
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2 INTRODUCTION Copyright © 2010–2012, Texas Instruments Incorporated
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