Datasheet

TLV320AIC3120
SLAS653A –FEBRUARY 2010–REVISED MAY 2012 www.ti.com
6.16 Control Registers, Pages 33–43: ADC DSP Engine Instruction RAM (32:63) Through
(352:383)
The structuring of the registers within pages 33–43 is identical to that of page 32. Only the instruction
numbers differ. The range of instructions within each page is listed in the following table.
Page Instructions
33 32 to 63
34 64 to 95
35 96 to 127
36 128 to 159
37 160 to 191
38 192 to 223
39 224 to 255
40 256 to 287
41 288 to 319
42 320 to 351
43 352 to 383
6.17 Control Registers, Page 64: DAC DSP Engine Instruction RAM (0:31)
Page 64 / Register 0 (0x00): Page Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0000 0000: Page 0 selected
0000 0001: Page 1 selected
...
1111 1110: Page 254 selected
1111 1111: Page 255 selected
Page 64 / Register 1 (0x01): Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Reserved. Write only the default value to this register
Page 64 / Register 2 (0x02): Inst_0(23:16)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX Instruction Inst_0(23:16) of DAC miniDSP
Page 64 / Register 3 (0x03): Inst_0(15:8)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Instruction Inst_0(15:8) of DAC miniDSP
Page 64 / Register 4 (0x04): Inst_0(7:0)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W XXXX XXXX Instruction Inst_0(7:0) of DAC miniDSP
6.17.1 Page 64 / Register 5 (0x05) Through Page 64 / Register 97 (0x61)
The remaining unreserved registers on page 64 are arranged in groups of three, with each group
containing the bits of one instruction. The arrangement is the same as that of registers 2–4 for instruction
0. Registers 5–7, 8–10, 11–13, ..., 95–97 contain instructions 1, 2, 3, ..., 31, respectively.
146 REGISTER MAP Copyright © 2010–2012, Texas Instruments Incorporated
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