Datasheet

T0146-07
WCLK
BCLK
DOUT
DIN
t (DO-BCLK)
d
t (WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
t
f
t
r
TLV320AIC3120
www.ti.com SLAS653A –FEBRUARY 2010–REVISED MAY 2012
3.4.3 DSP Timing in Master Mode
All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization.
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNITS
MIN MAX MIN MAX
t
d
(WS) WCLK delay 45 20 ns
t
d
(DO-BCLK) BCLK to DOUT delay 45 20 ns
t
s
(DI) DIN setup 8 8 ns
t
h
(DI) DIN hold 8 8 ns
t
r
Rise time 25 10 ns
t
f
Fall time 25 10 ns
Figure 3-3. DSP Timing in Master Mode
Copyright © 2010–2012, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 11
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