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TLV320AIC3120

www.ti.com

SLAS653A –FEBRUARY 2010–REVISED MAY 2012

Low-Power Mono Audio Codec With Embedded miniDSP

and Mono Class-D Speaker Amplifier

Check for Samples: TLV320AIC3120

1 INTRODUCTION

• Programmble PLL for Flexible Clock

1.1 Features

Generation

1234

• Mono Audio DAC With 95-dB SNR

• I

S, Left-Justified, Right-Justified, DSP, and

• Mono Audio ADC With 90-dB SNR

TDM Audio Interfaces

• Supports 8-kHz to 192-kHz Separate DAC and

• I

C Control With Register Auto-Increment

ADC Sample Rates

• Full Power-Down Control

• Instruction-Programmable Embedded miniDSP

• Power Supplies:

• Mono Class-D BTL Speaker Driver (2.5 W Into

– Analog: 2.7 V–3.6 V

4 Ω or 1.6 W Into 8 Ω) Output

– Digital Core: 1.65 V–1.95 V

• Mono Headphone/Lineout Outputs

– Digital I/O: 1.1 V–3.6 V

• One Differential or Three Single-Ended Inputs

– Class-D: 2.7 V–5.5V (SPKVDD ≥ AVDD)

With Mixing and Level Control

• 5-mm × 5-mm 32-QFN Package

• Microphone With Bias, Preamp PGA, and AGC

• Built-in Digital Audio Processing Blocks (PRB)

1.2 Applications

With User-Programmable Biquad, FIR Filters,

and DRC

• Portable Audio Devices

• Bass Boost/Treble/EQ With up to Five Biquads

• Mobile Internet Devices

for Record and up to Six Biquads for Playback

• eBooks

• Digital Mixing Capability

• Adaptive Filtering Applications

• Pin Control or Register Control for Digital

Playback Volume Control Settings

1.3 Description

The TLV320AIC3120 is a low-power, highly integrated, high-performance codec which features a mono

audio DAC and mono audio ADC.

The TLV320AIC3120 features a high-performance audio codec with 24-bit mono playback and mono

record functionality. The device integrates several analog features, such as a microphone interface,

headphone drivers, and speaker drivers. The TLV320AIC3120 has a fully programmable miniDSP for

digital audio processing. The digital audio data format is programmable to work with popular audio

standard protocols (I

S, left/right-justified) in master, slave, DSP, and TDM modes. Bass boost, treble, or

EQ can be supported by the programmable digital signal-processing blocks (PRB). An on-chip PLL

provides the high-speed clock needed by the digital signal-processing block. The volume level can be

controlled either by pin control or by register control. The audio functions are controlled using the I

C serial

bus.

The TLV320AIC3120 is available in a 32-pin QFN package. PurePath Studio™

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PurePath Studio is a trademark of Texas Instruments.

3MATLAB is a trademark of The MathWorks, Inc.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (155 pages)

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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Low-Power Mono Audio Codec With Embedded miniDSP and Mono Class-D Speaker Amplifier Check for Samples: TLV320AIC3120 1 INTRODUCTION 1.1 Features • Mono Audio DAC With 95-dB SNR • Mono Audio ADC With 90-dB SNR • Supports 8-kHz to 192-kHz Separate DAC and ADC Sample Rates • Instruction-Programmable Embedded miniDSP • Mono Class-D BTL Speaker Driver (2.5 W Into 4 Ω or 1.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 2 PACKAGE AND SIGNAL DESCRIPTIONS 2.1 Package/Ordering Information PRODUCT PACKAGE PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320AIC3120 QFN-32 RHB –40°C to 85°C 2.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 2-1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO.
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TLV320AIC3120 www.ti.com 3.2 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM (2) 2.7 3.3 3.6 Referenced to DVSS(2) 1.65 1.8 1.95 Referenced to HPVSS(2) 2.7 3.3 3.6 SPKVDD (1) Referenced to SPKVSS(2) 2.7 IOVDD Referenced to IOVSS(2) 1.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6V, DVDD = 1.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Digital Interpolation Filter Characteristics See Section 5.6.1.4 for DAC interpolation filter characteristics.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Electrical Characteristics (continued) At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6V, DVDD = 1.8 V, fS (audio) = 48 kHz, CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 Ω (Differential), 50 pF Output voltage Output, common-mode SNR Signal-to-noise ratio SPKVDD 3.
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TLV320AIC3120 www.ti.com 3.4 3.4.1 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Timing Characteristics I2S/LJF/RJF Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 3.4.2 www.ti.com I2S/LJF/RJF Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization.
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TLV320AIC3120 www.ti.com 3.4.3 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 DSP Timing in Master Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. WCLK td(WS) td(WS) tf BCLK tr td(DO-BCLK) DOUT tS(DI) th(DI) DIN T0146-07 PARAMETER td(WS) td(DO-BCLK) ts(DI) th(DI) tr tf WCLK delay BCLK to DOUT delay DIN setup DIN hold Rise time Fall time IOVDD = 1.1 V MIN MAX 45 45 8 8 25 25 IOVDD = 3.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 3.4.4 www.ti.com DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization.
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TLV320AIC3120 www.ti.com 3.4.5 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 I2C Interface Timing All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization. SDA tBUF tLOW tr tHIGH tf tHD;STA SCL tHD;STA tSU;DAT tHD;DAT STO tSU;STO tSU;STA STA STA STO T0295-02 PARAMETER fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb SCL clock frequency Hold time (repeated) START condition.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 4 TYPICAL PERFORMANCE 4.1 Audio ADC Performance AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 20 20 AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V 0 −20 −20 −40 −40 Amplitude − dBFS Amplitude − dBFS 0 −60 −80 −100 −60 −80 −100 −120 −120 −140 −140 −160 −160 0 5 10 15 20 0 5 f − Frequency − kHz 10 15 G018 G019 Figure 4-1.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 AMPLITUDE vs FREQUENCY SNR vs PGA CHANNEL GAIN 0 100 AVDD = HPVDD = 3.3 V IOVDD = SPLVDD = 3.3 V DVDD = 1.8 V −10 Diff = 10k 90 −30 85 −40 80 SNR − dB Amplitude − dBFS −20 95 −50 −60 Diff = 20k Diff = 40k 75 SE = 10k 70 −70 65 −80 60 −90 55 SE = 20k SE = 40k −100 0 50 100 150 50 −10 200 0 10 f − Frequency − kHz G028 40 50 60 70 Figure 4-6.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − dB 0 HPVDD = 2.7 V CM = 1.35 V −10 −20 −30 −40 HPVDD = 3 V CM = 1.5 V −50 HPVDD = 3.3 V CM = 1.65 V −60 HPVDD = 3.6 V CM = 1.8 V −70 IOVDD = 3.3 V DVDD = 1.8 V Gain = 9 dB RL = 16 Ω −80 −90 −100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 PO − Output Power − W G025 Figure 4-9. Headphone Output Power 4.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 0 AVDD = HPVDD = 3.3 V IOVDD = 3.3 V SPKVDD = 5.5 V DVDD = 1.8 V RL = 8 Ω −10 −20 THD+N − Total Harmonic Distortion + Noise − dB THD+N − Total Harmonic Distortion + Noise − dB 0 Driver Gain = 18 dB −30 Driver Gain = 24 dB −40 Driver Gain = 12 dB −50 Driver Gain = 6 dB −60 −70 0.0 0.5 1.0 1.5 2.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 4.5 www.ti.com MICBIAS Performance VOLTAGE vs CURRENT 3.5 3.0 Micbias = AVDD (3.3 V) V − Voltage − V 2.5 Micbias = 2.5 V 2.0 Micbias = 2 V 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 I − Current − mA G016 Figure 4-16.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5 APPLICATION INFORMATION 5.1 Typical Circuit Configuration +3.3VA SVDD 0.1 mF 22 mF 0.1 mF 22 mF 0.1 mF 0.1 mF 10 mF 10 mF 3.3 V SPKVDD SPKVDD SPKVSS SPKVSS HPVDD AVDD AVSS HPVSS 2.7 kW ´ 2 SPKP SPKP 8-W or 4-W Speaker SPKM SPKM SDA SCL 0.1 mF MIC1LM 2.2 kW GPIO1 0.1 mF TLV320AIC3120 MIC1LP MCLK VOL/MICDET DOUT 2.2 kW MICBIAS WCLK 0.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 • • • • • • www.ti.com Class-D mono amplifier for 4-Ω or 8–Ω speakers Pin-controlled or register-controlled volume level Power-down de-pop and power-up soft start Analog inputs I2C control interface Power-down control block Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C interface is used to write to the control registers to configure the device.
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TLV320AIC3120 www.ti.com 5.2.2 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Audio Analog I/O The TLV320AIC3120 has a mono audio DAC and a mono ADC. It supports a wide range of analog interfaces to support different headsets and analog outputs. The TLV320AIC3120 has features to interface output drivers (8-Ω, 16-Ω, 32-Ω) and a microphone PGA with AGC control. 5.3 miniDSP The TLV320AIC3120 features two miniDSP cores.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com AOSR = 64, Processing Block = PRB_R11 (Decimation Filter B) Power consumption = 7.99 mW Table 5-2. PRB_R11 Alternative Processing Blocks, 7.99 mW 5.4.2 Processing Block Filter Estimated Power Change (mW) PRB_R4 A 0.43 PRB_R5 A 0.67 PRB_R6 A 0.66 PRB_R10 B –0.14 PRB_R12 B 0.04 ADC, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V AOSR = 128, Processing Block = PRB_R4 (Decimation Filter A) Power consumption = 6.77 mW Table 5-3.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B) Power consumption = 15.54 mW Table 5-6. PRB_P12 Alternative Processing Blocks, 15.54 mW 5.4.4 Processing Block Filter Estimated Power Change (mW) PRB_P4 A 0.37 PRB_P5 A 1.23 PRB_P6 A 1.15 PRB_P13 B 0.43 PRB_P14 B 0.13 PRB_P15 B 0.85 PRB_P16 B 0.21 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-9. MICBIAS Settings D1 D0 0 0 MICBIAS output is powered down. FUNCTIONALITY 0 1 MICBIAS output is powered to 2 V. 1 0 MICBIAS output is powered to 2.5 V. 1 1 MICBIAS output is powered to AVDD. During normal operation, MICBIAS can be set to 2.5 V for better performance.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 register 82, bit D7 and page 1 / register 47, bit D7. Disabling the MIC PGA sets the gain to 0 dB. Muting the ADC causes the digital output to mute so that the output value remains fixed. When soft-stepping is enabled, the CODEC_CLKIN signal must stay active until after the ADC power-down register is written, in order to ensure that soft-stepping to mute has had time to complete.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5.5.2 www.ti.com Automatic Gain Control (AGC) The TLV320AIC3120 includes automatic gain control (AGC) for the microphone inputs. AGC can be used to maintain nominally constant output-signal amplitude when recording speech signals. This circuitry automatically adjusts the MIC PGA gain as the input signal becomes overly loud or very soft, such as when a person speaking into a microphone moves closer to or farther from the microphone.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-11.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com One example of AGC code follows, but actual use of code should be verified based on application usage. Note that the AGC code should be set up before powering up the ADC.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-12.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A From Delta-Sigma Modulator or Digital Microphone AGC Gain Compen sation st Filter A 1 Order IIR ´ 25-Tap FIR To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-5. Signal Chain for PRB_R6 5.5.4.2.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5.5.4.2.7 First-Order IIR, AGC, Filter C From Delta-Sigma Modulator or Digital Microphone Filter C ´ AGC Gain Compen sation st 1 Order IIR To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 5-9. Signal Chain for PRB_R16 5.5.4.2.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com The coefficients of these filters are each 16 bits wide, in 2s-complement format, and occupy two consecutive 8-bit registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF), as shown in Figure 5-12. 2 –15 2 2 –4 –1 Bit Bit Largest Positive Number: = 0.111111111111111111 = 0.999969482421875 = 1.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-14. ADC Biquad Filter Coefficients (continued) Filter Filter Coefficient Biquad C Biquad D Biquad E Filter Coefficient RAM Location Default (Reset) Values N0 Page 4 / register 34 and page 4 / register 35 0x7FFF (decimal 1.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-15. ADC FIR Filter Coefficients (continued) Filter Coefficient Default (Reset) Values (1) FIlter Coefficient RAM Location Fir12 Page 4 / register 38 and page 4 / register 39 0x0000 Fir13 Page 4 / register 40 and page 4 / register 41 0x0000 Fir14 Page 4 / register 42 and page 4 / register 43 0x0000 Fir15 Page 4 / register 44 and page 4 / register 45 0x7FFF (decimal 1.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 ADC Channel Response for Decimation Filter A (Red Line Corresponds to –73 dB) 0 –10 Magnitude – dB –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Frequency Normalized to fS 2 Figure 5-13. ADC Decimation Filter A, Frequency Response 5.5.4.4.2 Decimation Filter B Filter B is intended to support sampling rates up to 96 kHz at an oversampling ratio of 64. Table 5-17.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.5.4.4.3 Decimation Filter C Filter C along with an AOSR of 32 is specially designed for 192-ksps operation for the ADC. The pass band, which extends up to 0.11 × fS (corresponding to 21 kHz), is suited for audio applications. Table 5-18. ADC Decimation Filter C, Specifications Parameter Condition Value (Typical) Unit Filter gain from 0 to 0.11 fS 0…0.11 fS ±0.033 dB Filter gain from 0.28 fS to 16 fS 0.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Record - Paused Volume Ramp Down Soft Mute ADC Volume Ramp Down WAIT Time (A) Wait (A) ms For fS = 32 kHz ® Wait 10 ms (min) For fS = 48 kHz ® Wait 8 ms (min) ADC Power Down Update Digital Filter Coefficients ADC Volume Ramp Up Time (B) For fS = 32 kHz ® 10 ms For fS = 48 kHz ® 8 ms ADC Power UP Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Record - Continue F0023-02 Figure 5-16.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com D-S ADC Signal Processing Blocks DOUT DIG_MIC_IN Mono ADC CIC Filter ADC_MOD_CLK SDIN GPIO1 Figure 5-17. Digital Microphone in the TLV320AIC3120 The TLV320AIC3120 outputs internal clock ADC_MOD_CLK on the GPIO1 pin (page 0 / register 51, bits D5–D2 = 1010). This clock can be connected to the external digital microphone device. The single-bit output of the external digital microphone device can be connected to the DIN pin.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Mode B To choose mode B, page 0 / register 102, bit D5 must be programmed to 1. In dc-measurement mode B, a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0 / register 102, bits D4–D0. The nature of the filter is given in Table 5-19. Table 5-19. DC Measurement Bandwidth Settings D:Page 0 / Register 102, Bits D4–D0 –3-dB BW (kHz) –0.5-dB BW (kHz) 1 688.44 236.5 2 275.97 96.334 3 127.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Based on the identified filter type and the required signal processing capabilities, the appropriate processing block can be determined from the list of available processing blocks (PRB_R4 to PRB_R18). Based on the available master clock, the chosen AOSR and the targeted sampling rate, the clock divider values NADC and MADC can be determined. If necessary, the internal PLL can add a large degree of flexibility.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 4. Program ADC (a) Set register page to 0 (b) Power up ADC channel (c) Unmute digital volume control and set gain A detailed example can be found in Section 5.5.9. 5.5.9 Example Register Setup to Record Analog Data Through ADC to Digital Out A typical EVM I2C register control script follows to show how to set up the TLV320AIC3120 ADC in record mode with fS = 44.1 kHz and MCLK = 11.2896 MHz.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 # # # w # # # # # # w # # # # # # w # # w # # # # # w # # w # # # # w # 5.6 www.ti.com 3. Program Analog Blocks (a) Set register Page to 1 30 00 01 (b) Program MICBIAS if applicable Programmed MICBIAS always on, 2.5V w 30 2E 0A Micbias = AVDD 30 2e 0a (c) Program MicPGA (d) Routing of inputs/common mode to ADC input (e) Unmute analog PGAs and set analog gain MICPGA P = MIC1LP 20kohm 30 30 80 MICPGA M - CM 20kohm 30 31 80 4.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 DAC power up is controlled by writing to page 0 / register 63, bit D7 for the mono channel. The monochannel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7. 5.6.1.1 DAC Processing Blocks The TLV320AIC3120 implements signal-processing capabilities and interpolation filtering via processing blocks.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.6.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D BiQuad E Interp. Filter A,B BiQuad F HPF ´ to Modulator Digital Volume Ctrl DRC Figure 5-20. Signal Chain for PRB_P5 and PRB_P15 5.6.1.2.3 Six Biquads, First-Order IIR, Filter A or B BiQuad A IIR from Interface BiQuad B BiQuad C BiQuad D BiQuad E Interp.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5.6.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C BiQuad A IIR BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to Modulator from Interface HPF Digital Volume Ctrl DRC Figure 5-25. Signal Chain for PRB_P21 5.6.1.2.8 Four Biquads, First-Order IIR, Filter C IIR from Interface BiQuad A BiQuad B BiQuad C BiQuad D Interp. Filter C ´ to modulator Digital Volume Ctrl Figure 5-26. Signal Chain for PRB_P22 5.6.1.2.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use. Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use. While the device is running, coefficient updates are always made to the buffer not in use by the DAC, regardless of the buffer to which the coefficients have been written.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-21.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-23. DAC Biquad Filter Coefficients (continued) Filter Biquad B Biquad C Biquad D Biquad E Biquad F 5.6.1.4 Coefficient Mono DAC Channel N0 Page 8 / register 12 and page 8 / register 13 0x7FFF (decimal 1.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-24. Specification for DAC Interpolation Filter A Parameter Condition Value (Typical) Unit Filter-gain pass band 0… 0.45 fS ±0.015 dB Filter-gain stop band 0.55 fS… 7.455 fS –65 dB 21/fS s Filter group delay DAC Channel Response for Interpolation Filter A (Red Line Corresponds to –65 dB) 0 –10 Magnitude – dB –20 –30 –40 –50 –60 –70 –80 –90 1 2 5 6 3 4 Frequency Normalized to fS 7 Figure 5-28.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.6.1.4.3 Interpolation Filter C Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × fS (corresponds to 80 kHz), more than sufficient for audio applications. Table 5-26. Specification for DAC Interpolation Filter C Parameter Condition Value (Typical) Unit Filter-gain pass band 0…0.35 fS ±0.03 dB Filter-gain stop band 0.6 fS…1.
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TLV320AIC3120 www.ti.com 5.6.3 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Volume-Control Pin The range of voltages used by the 7-bit SAR ADC is shown in the Electrical Characteristics table. The volume-control pin is not enabled by default, but it can be enabled by writing 1 to page 0 / register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if page 0 / register 116, bit D7 = 0.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com AVDD R1 34.8 kW P1 25 kW VOL/MICDET 1 mF R2 9.76 kW AVSS Figure 5-31. Example Analog Volume Control Circuit to VOL/MICDET Pin Table 5-28. VOL/MICDET Pin Gain Scaling 5.6.4 ADC VOLTAGE for AVDD = 3.3 V (V) DIGITAL GAIN RANGE (dB) 0 0 V to 1.65 V 18 dB to –63 dB 7.68 0.386 V to 1.642 V 3 dB to –63 dB 0.463 V to 1.649 V 0 dB to –63 dB R1 (kΩ) P1 (kΩ) R2 (kΩ) 25 25 33 25 34.8 25 9.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-29.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5.6.4.4 www.ti.com DRC Attack Rate When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain applied in the DAC digital volume control is progressively reduced to avoid the signal from saturating the channel. This process of reducing the applied gain is called attack.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Script # Go to Page 0 w 30 00 00 # DAC => 12 db gain mono w 30 41 18 # DAC => DRC Enabled, Threshold = -24 db, Hysteresis = 3 dB w 30 44 7F # DRC Hold = 0 ms, Rate of Changes of Gain = 0.5 dB/Fs' w 30 45 00 #Attack Rate = 1.9531e-4 dB/Frame , DRC Decay Rate =2.4414e-5 dB/Frame w 30 46 B6 # Go to Page 9 w 30 00 09 # DRC HPF w 30 0E 7F AB 80 55 7F 56 # DRC LPF W 30 14 00 11 00 11 7F DE 5.6.4.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com removal event is detected. These sticky flags are set by the event occurrence, and are reset only when read. This requires polling page 0 / register 44. To avoid polling and the associated overhead, the TLV320AIC3120 also provides an interrupt feature whereby the events can trigger the INT1 and/or INT2 interrupts. These interrupt events can be routed to one of the digital output pins. See Section 5.6.4.8 for details.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 The two registers used for programming the 16-bit sine-wave coefficient are page 0 / register 76 and page 0 / register 77. The two registers used for programming the 16-bit cosine-wave coefficient are page 0 / register 78 and page 0 / register 79. This coefficient resolution allows virtually any frequency of sine wave in the audio band to be generated, up to fS/2.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Following the DAC, the signal can be further scaled by the analog output volume control and poweramplifier level control. The beep generator is used for the key-click function. A single beep is generated by writing to page 0 / register 71, bit D7. After the programmed beep length has finished, register 71, bit D7 is reset back to zero. 5.6.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Play - Paused Volume Ramp Down Soft Mute Wait (A) ms DAC Volume Ramp Down WAIT Time (A) For fS = 32 kHz ® Wait 25 ms (min) DAC Power Down Update Digital Filter Coefficients For fS = 48 kHz ® Wait 20 ms (min) DAC Volume Ramp Up Time (B) For fS = 32 kHz ® 25 ms DAC Power UP For fS = 48 kHz ® 20 ms Wait 20 ms Restore Previous Volume Level (Ramp) in (B) ms Play - Continue F0024-02 Figure 5-33.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5.6.9.1 www.ti.com Analog Output Volume Control The output volume control can be used to fine-tune the level of the mixer amplifier signal supplied to the headphone driver or the speaker driver. This architecture supports separate and concurrent volume levels for each of the four output drivers. This volume control can also be used as part of the output pop-noise reduction scheme.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-33. Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) (1) Register Value D6–D0 (1) Analog Gain (dB) Register Value D6–D0 Analog Gain (dB) Register Value D6–D0 Analog Gain (dB) Register Value D6–D0 Analog Gain (dB) 0 0.0 30 –15.0 60 –30.1 90 –45.2 1 –0.5 31 –15.5 61 –30.6 91 –45.8 2 –1.0 32 –16.0 62 –31.1 92 –46.2 3 –1.5 33 –16.5 63 –31.6 93 –46.7 4 –2.0 34 –17.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 5.6.10 Analog Outputs Various analog routings are supported for playback. All the options can be conveniently viewed on the functional block diagram, Figure 1-1. 5.6.10.1 Headphone Drivers The TLV320AIC3120 features a mono headphone driver (HPOUT) that can deliver up to 30 mW per channel, at 3.3-V supply voltage, into a 16-Ω load.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 If shutdown occurs due to an overcurrent condition, then the device requires a reset to re-enable the output stage. Resetting can be done in two ways. First, the device master reset can be used, which requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of the registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device settings.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock divider values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of flexibility. In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by MDAC, NDAC, and DOSR must be equal to the DAC sampling rate DAC_fS.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5. Power up DAC (a) Set register page to 0 (b) Power up DAC channels and set digital gain (c) Unmute digital volume control A detailed example can be found in Section 5.6.13. 5.6.13 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs A typical EVM I2C register control script follows to show how to set up the TLV320AIC3120 DAC in playback mode with fS = 44.1 kHz and MCLK = 11.2896 MHz.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 # # # w w w w # # # # # w # # # w # # # w # # # # w # # # # w # w # # # # w # w # w # w # # # # # # # w # # # # w # # w # # # # w 66 www.ti.com (g) Program the processing block to be used select DAC DSP Processing Block PRB_P16 30 3C 10 30 00 08 30 01 04 30 00 00 3. Program analog blocks (a) Set register page to 1 30 00 01 (b) Program common-mode voltage (defalut = 1.
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TLV320AIC3120 www.ti.com 5.7 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 CLOCK Generation and PLL The TLV320AIC3120 supports a wide range of options for generating clocks for the ADC and DAC sections as well as the interface and other control blocks shown in Figure 5-34. The clocks for ADC and DAC require a source reference clock. This clock can be provided on variety of device pins, such as MCLK, BCLK, or GPIO1 pins.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 DAC _ MOD _ CLK = DAC _ fS = www.ti.com CODEC _ CLKIN NDAC ´ MDAC CODEC _ CLKIN NDAC ´ MDAC ´ DOSR ADC _ MOD _ CLK = ADC _ fS = CODEC _ CLKIN NADC ´ MADC CODEC _ CLKIN NADC ´ MADC ´ AOSR (8) Table 5-35.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 DAC_MOD_CLK ADC_MOD_CLK ADC_CLK DAC_CLK BDIV_CLKIN N = 1, 2, ..., 127, 128 ÷N BCLK Figure 5-35. ¿ In the mode when the TLV320AIC3120 is configured to drive the BCLK pin (page 0 / register 27, bit D3 = 1), it can be driven as a divided value of BDIV_CLKIN. The division value can be programmed in page 0 / register 30, bits D6–D0 from 1 to 128.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 5-36. Maximum TLV320AIC3120 Clock Frequencies DVDD ≥ 1.65 V Clock 5.7.1 CODEC_CLKIN ≤ 110 MHz ADC_CLK (ADC DSP clock) ≤ 49.152 MHz ADC_miniDSP_CLK ≤ 24.576 MHz ADC_MOD_CLK 6.758 MHz ADC_fS 0.192 MHz DAC_CLK (DAC DSP clock) ≤ 49.152 MHz DAC_miniDSP_CLK ≤ 49.152 MHz with DRC disabled ≤ 48 MHz with DRC enabled DAC_MOD_CLK 6.758 MHz DAC_fS 0.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 4 ≤ R × J ≤ 259 When the PLL is enabled and D ≠ 0, the following conditions must be satisfied for PLL_CLKIN: PLL _ CLKIN 10 MHz £ £ 20 MHz P • (11) 80 MHz ≤ PLL_CLKIN × J.D × R/P ≤ 110 MHz R=1 The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a general-purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is available typically after 10 ms.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Powered on if internal oscillator is selected Internal Oscillator ÷8 0 Interval timers MCLK Programmable Divider Used for de-bounce time for headset detection logic, various power up timers and for generation of interrupts 1 P3/R16, Bits D6-D0 P3/R16, Bit D7 Figure 5-37. Interval Timer Clock Selection 5.8 Digital Audio and Control Interface 5.8.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 The TLV320AIC3120 also includes a feature to offset the position of start of data transfer with respect to the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in page 0 / register 28. The TLV320AIC3120 also has the feature of inverting the polarity of the bit clock used for transferring the audio data as compared to the default clock polarity used.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 N N N - - 1 2 3 0 3 LD(n) 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data LD(n+1) RD(n) = n'th sample of right channel data Figure 5-39.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA N N N - - 1 2 3 3 2 1 N N N - - 1 2 3 0 LD(n) 3 2 1 N N N - - 1 2 3 0 RD(n) LD(n) = n'th sample of left channel data 3 LD(n+1) RD(n) = n'th sample of right channel data Figure 5-42.
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TLV320AIC3120 www.ti.com 0 LSB 1 2 MSB n–1 n–2 n–3 0 LSB 1 2 MSB n–1 n–2 n–3 0 LSB 0 LSB n–1 n–2 n–3 1 2 n–1 n–2 n–3 MSB DOUT BCLK WCLK 1 Clock Before MSB 1/fS MSB 2 1 ADC Mono Channel (D0) ADC Mono Channel (D0) ADC Mono Channel (D1) 1/fS ADC Mono Channel (D1) n–1 T0202-03 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Figure 5-45.
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TLV320AIC3120 www.ti.com 5.8.1.4 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 DSP Mode The audio interface of the TLV320AIC3120 can be put into DSP mode by programming page 0 / register 27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the leftchannel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5.8.2 www.ti.com Primary and Secondary Digital Audio Interface Selection The audio serial interface on the TLV320AIC3120 has extensive I/O control to allow communication with two independent processors for audio data. Only one processor can communicate with the device one at any given time. This feature is enabled by register programming of the various pin selections.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 5-39.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 5.8.3.1 www.ti.com I2C Control Mode The TLV320AIC3120 supports the I2C control protocol and responds to the I2C address of 0011.000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 SCL DA(6) SDA Start (M) DA(0) 7-bit Device Address (M) RA(7) Write (M) Slave Ack (S) RA(0) 8-bit Register Address (M) D(7) Slave Ack (S) D(0) 8-bit Register Data (M) Slave Ack (S) Stop (M) (M) => SDA Controlled by Master (S) => SDA Controlled by Slave Figure 5-50.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 6 REGISTER MAP 6.1 TLV320AIC3120 Register Map All features on this device are addressed using the I2C bus. All of the writable registers can be read back. However, some registers contain status information or data, and are available for reading only. The TLV320AIC3120 contains several pages of 8-bit registers, and each page can contain up to 128 registers. The register pages are divided up based on functional blocks for this device.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 2 (0x02): Reserved READ/ WRITE R RESET VALUE XXXX XXXX D7-D2 D1 READ/ WRITE R R RESET VALUE XXXX XX 1 D0 R/W X BIT D7–D0 DESCRIPTION Reserved. Do not write to this register. Page 0 / Register 3 (0x03): OT FLAG BIT DESCRIPTION Reserved. Do not write to these bits. 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up 1: Normal operation Reserved.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-2. Page 0 / Register 7 (0x07): PLL D-VAL MSB (1) BIT D7–D6 D5–D0 (1) READ/ WRITE R/W R/W RESET VALUE 00 00 0000 DESCRIPTION Reserved. Write only zeros to these bits. PLL fractional multiplier D-Val MSB bits D[13:8] Note that this register will be updated only when page 0 / register 8 is written immediately after page 0 / Register 7.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 15 (0x0F): DAC IDAC_VAL (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 1000 0000 DESCRIPTION 0000 0000: 0000 0001: 0000 0010: ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 21 (0x15): ADC IADC Value (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 1000 0000 DESCRIPTION 0000 0000: Reserved 0000 0001: Number of instruction 0000 0010: Number of instruction ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4–D2 R/W 000 D1–D0 R/W 00 D7–D5 READ/ WRITE R/W RESET VALUE 000 D4 D3 R/W R/W 0 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3–D2 R/W 00 D1 R/W 0 D0 R/W 0 BIT DESCRIPTION 000: Secondary BCLK is obtained from GPIO1 pin.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 35 (0x23): Reserved READ/ WRITE R/W RESET VALUE XXXX XXXX D7 READ/ WRITE R RESET VALUE 1 D6 R 0 D5 (1) R 0 D4–D0 R X XXXX BIT D7–D0 DESCRIPTION Reserved. Write only zeros to these bits.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 40 Through Page 0 (0x28) / Register 43 (0x2B): Reserved READ/ WRITE R/W RESET VALUE XXXX XXXX READ/ WRITE R RESET VALUE 0 D6 (1) D5 (1) R R 0 X D4 (1) R X D3 (1) R 0 D2 (1) D1 (1) R R 0 0 D0 (1) R 0 BIT D7–D0 DESCRIPTION Reserved. Write only the reset value to these bits.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 49 (0x31): INT2 Control Register D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4 R/W 0 D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 BIT DESCRIPTION 0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt. 1: Headset-insertion detect interrupt is used in the generation of INT2 interrupt. 0: Button-press detect interrupt is not used in the generation of INT2 interrupt.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 61 (0x3D): ADC Processing Block / miniDSP Selection BIT D7–D5 D4–D0 READ/ WRITE R/W R/W RESET VALUE 000 0 0100 DESCRIPTION Reserved. Write only default values. 0 0000: ADC miniDSP is used for signal processing. 0 0001–0 0011: Reserved. Do not use. 0 0100: ADC signal-processing block PRB_R4 0 0101: ADC signal-processing block PRB_R5 0 0110: ADC signal-processing block PRB_R6 0 0111–01001: Reserved. Do not use.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 65 (0x41): DAC Volume Control BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0111 1111–0011 0001: Reserved. Do not write these sequences to these bits. 0011 0000: DAC digital gain = 24 dB 0010 1111: DAC digital gain = 23.5 dB 0010 1110: DAC digital gain = 23 dB ... 0011 0100: DAC digital gain = 18 dB 0010 0011: DAC digital gain = 17.5 dB 0010 0010: DAC digital gain = 17 dB ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 68 (0x44): DRC Control 1 D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 1 D5 D4–D2 R/W R/W 1 011 D1–D0 R/W 11 BIT DESCRIPTION Reserved. Write only the reset value to these bits. 0: DRC disabled 1: DRC enabled Reserved. Write only reset value.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 71 (0x47): Beep Generator D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D0 R/W R/W 0 00 0000 BIT (1) (1) DESCRIPTION 0: Beep generator is disabled. 1: Beep generator is enabled (self-clearing based on beep duration). Reserved. Write only reset value. 00 0000: Beep volume control = 2 dB 00 0001: Beep volume control = 1 dB 00 0010: Beep volume control = 0 dB 00 0011: Beep volume control = –1 dB ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 80: Reserved READ/ WRITE R/W RESET VALUE 0 D7 READ/ WRITE R/W RESET VALUE 0 D6 D5–D4 R/W R/W 0 00 D3 R/W 0 D2 D1–D0 R/W R/W 0 00 D7 READ/ WRITE R/W RESET VALUE 1 D6–D4 R/W 000 D3–D0 R/W 0000 READ/ WRITE R/W RESET VALUE 0 000 0000 BIT D7–D0 DESCRIPTION Reserved. Page 0 / Register 81 (0x51): ADC Digital Mic BIT DESCRIPTION 0: ADC channel is powered down. 1: ADC channel is powered up.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 86 (0x56): AGC Control 1 D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D0 R/W 0000 D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D1 R/W 00 000 D0 R/W 0 READ/ WRITE R/W R/W RESET VALUE 0 111 1111 D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 BIT DESCRIPTION 0: AGC disabled 1: AGC enabled 000: AGC target level = –5.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 90 (0x5A): AGC Decay Time D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 BIT DESCRIPTION 0000 0: AGC decay time = 1 × (512/fS) 0000 1: AGC decay time = 3 × (512/fS) 0001 0: AGC decay time = 5 × (512/fS) 0001 1: AGC decay time = 7 × (512/fS) 0010 0: AGC decay time = 9 × (512/fS) ...
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 0 / Register 93 (0x5D): AGC Gain-Applied Reading BIT D7–D0 READ/ WRITE R RESET VALUE XXXX XXXX DESCRIPTION 1110 1000: 1110 1001: ... 0000 0000: ... 0111 0110: 0111 0111: ADC channel AGC gain = –12 dB ADC channel AGC gain = –11.5 dB ADC channel AGC gain = 0 dB ADC channel AGC gain = 59 dB ADC channel AGC gain = 59.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 0 / Register 106: (0x6A) ADC DC Measurement Output 3 BIT D7–D0 READ/ WRITE R RESET VALUE 0000 0000 DESCRIPTION ADC DC Measurement Output (7:0) Page 0 / Register 107 (0x0B) Through Page 0 / Register 115 (0x73): Reserved READ/ WRITE R/W RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D4 R/W 00 D3 D2–D0 R/W R/W 0 000 READ/ WRITE R/W R RESET VALUE 0 XXX XXXX BIT D7–D0 DESCRIPTION Reserved.
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TLV320AIC3120 www.ti.com 6.3 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls and MISC Logic Related Programmabilities Page 1 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 1 / Register 36 (0x24): Analog Volume to HPOUT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 READ/ WRITE R/W RESET VALUE 0111 1111 D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 111 1111 READ/ WRITE R/W RESET VALUE 0111 1111 BIT DESCRIPTION 0: Analog volume control is not routed to HPOUT output driver. 1: Analog volume control is routed to HPOUT output driver.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 42 (0x2A): Class-D Output Driver D7–D5 D4–D3 READ/ WRITE R/W R/W RESET VALUE 000 00 D2 R/W 0 D1 D0 R/W R 0 0 READ/ WRITE R/W RESET VALUE XXXX XXXX D7–D5 READ/ WRITE R/W RESET VALUE 001 D4–D3 R/W 00 D2 R/W 0 D1–D0 R/W 00 BIT DESCRIPTION Reserved. Write only zeros to these bits.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 1 / Register 46 (0x2E): MICBIAS D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 D3 R/W R/W 000 0 D2 D1–D0 R/W R/W 0 00 D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 000 0000 BIT DESCRIPTION 0: Device software power down is not enabled. 1: Device software power down is enabled. Reserved. Write only zeros to these bits. 0: Programmed MICBIAS is not powered up if headset detection is enabled but headset is not inserted.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Page 1 / Register 50 (0x32): Input CM Settings D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5 R/W 0 D4–D1 D0 R/W R 0000 0 READ/ WRITE R/W RESET VALUE XXXX XXXX BIT DESCRIPTION 0: MIC1LP input is floating, if it is not used for the MIC PGA and analog bypass. 1: MIC1LP input is connected to CM internally, if it is not used for the MIC PGA and analog bypass.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 The remaining page-4 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320AIC3111. Reserved registers should not be written to. The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-3.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-3.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-3.
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TLV320AIC3120 www.ti.com 6.6 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127) Default values shown for this page only become valid 100 μs following a hardware or software reset. Table 6-4. Page 5 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-5.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-5.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-5.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-6.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-6.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-6.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-6.
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TLV320AIC3120 www.ti.com 6.8 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127) Default values shown for this page only become valid 100 μs following a hardware or software reset. Table 6-7. Page 9 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-8.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-8.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-8.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-10.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-10.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-10.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com The remaining page-11 registers are either reserved registers or are used for setting coefficients for the various filters in the TLV320AIC3111. Reserved registers should not be written to. The filter coefficient registers are arranged in pairs, with two adjacent 8-bit registers containing the 16-bit coefficient for a single filter.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-12.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-12.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 6.11 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63) Default values shown for this page only become valid 100 μs following a hardware or software reset. Table 6-13. Page 12 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-14.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-14.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-14.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-14. Page 12 Registers (continued) REGISTER NUMBER RESET VALUE 125 (0x7D) 0000 0000 Coefficient C62(7:0) of DAC miniDSP (DAC buffer B) 126 (0x7E) 0000 0000 Coefficient C63(15:8) of DAC miniDSP (DAC buffer B) 127 (0x7F) 0000 0000 Coefficient C63(7:0) of DAC miniDSP (DAC buffer B) REGISTER NAME 6.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-16.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-16.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-16.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-18.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-18.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-18.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 6.14 Control Registers, Page 15: DAC Programmable Coefficients RAM Buffer B (193:255) Default values shown for this page only become valid 100 μs following a hardware or software reset. Table 6-19. Page 15 / Register 0 (0x00): Page Control Register BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-20.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Table 6-20.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Table 6-20.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com 6.16 Control Registers, Pages 33–43: ADC DSP Engine Instruction RAM (32:63) Through (352:383) The structuring of the registers within pages 33–43 is identical to that of page 32. Only the instruction numbers differ. The range of instructions within each page is listed in the following table.
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TLV320AIC3120 www.ti.com SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 Page 64 / Register 98 (0x62) Through Page 64 / Register 127 (0x7F): Reserved BIT D7–D0 READ/ WRITE R/W RESET VALUE XXXX XXXX DESCRIPTION Reserved. Write only the default value to these registers. 6.18 Control Registers, Pages 65–95: DAC DSP Engine Instruction RAM (32:63) Through (992:1023) The structuring of the registers within pages 65–95 is identical to that of page 64. Only the instruction numbers differ.
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TLV320AIC3120 SLAS653A – FEBRUARY 2010 – REVISED MAY 2012 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision Original (February 2010) to Revision A • • • • • • • • • • • • • • • • • • 148 Page Added PGA Gain table to data sheet ......................................................................................... 24 Added PRB_P25 and values to table 5-20. ....................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV320AIC3120IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TLV320AIC3120IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC3120IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 TLV320AIC3120IRHBT VQFN RHB 32 250 210.0 185.0 35.
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