Datasheet

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• PLL: On or Off
• P,R,J,D: PLL configuration
• NADC, MADC: ADC clock dividers
• AOSR: ADC over-sampling factor
• FsADC: ADC sampling rate
• NDAC, MDAC: DAC clock dividers
• DOSR: DAC over-sampling factor
• FsDAC: DAC sampling rate
Click the Advanced … button to show the advanced clock settings dialog.
Figure 8. Advanced Clock Settings.
The advanced clock settings dialog gives direct access to the PLL and codec clock dividers. It will
recalculate the clock results dynamically whenever a parameter is changed.
The internally generated bit clock signal (BCLK) can be derived from several sources and divided by an
integer number. Select the desired source with the Source drop down box, choose the divisor and enable
power to the divider, if required.
It is possible to put out a clock signal CLKOUT. Select the clock source, the divider and the destination pin
using the advanced clock settings dialog.
SLAU285 – July 2009 TLV320AIC3111 EVM 13
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