Datasheet

TLV320AIC3110
SLAS647B –DECEMBER 2009–REVISED MAY 2012 www.ti.com
Page 0 / Register 53 (0x35): DOUT (OUT Pin) Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D5 R/W 000 Reserved
D4 R/W 1 0: DOUT bus keeper enabled
1: DOUT bus keeper disabled
D3–D1 R/W 001 000: DOUT disabled (output buffer powered down)
001: DOUT = primary DOUT output for codec interface
010: DOUT = general-purpose output
011: DOUT = CLKOUT output
100: DOUT = INT1 output
101: DOUT = INT2 output
110: DOUT = secondary BCLK output for codec interface
111: DOUT = secondary WCLK output for codec interface
D0 R/W 0 0: DOUT general-purpose output value = 0
1: DOUT general-purpose output value = 1
Page 0 / Register 54 (0x36): DIN (IN Pin) Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D3 R/W 0000 0 Reserved
D2–D1 R/W 01 00: DIN disabled (input buffer powered down)
01: DIN enabled (can be used as DIN for codec interface, Dig_Mic_In or in ClockGen block)
10: DIN is used as general-purpose input (GPI)
11: Reserved
D0 R X DIN input-buffer value
Page 0 / Register 55–59 : Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to these registers.
Page 0 / Register 60 (0x3C): DAC Processing Blocks Selection
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D5 R/W 000 Reserved. Write only default value.
D4–D0 R/W 0 0001 0 0000: Reserved. Write only reset value.
0 0001: DAC signal-processing block PRB_P1
0 0010: DAC signal-processing block PRB_P2
0 0011: DAC signal-processing block PRB_P3
0 0100: DAC signal-processing block PRB_P4
...
1 1000: DAC signal-processing block PRB_P24
1 1001: DAC signal-processing block PRB_P25
1 1010–1 1111: Reserved. Do not use.
92 REGISTER MAP Copyright © 2009–2012, Texas Instruments Incorporated
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