Datasheet

TLV320AIC3110
SLAS647B –DECEMBER 2009–REVISED MAY 2012 www.ti.com
Page 0 / Register 29 (0x1D): Codec Interface Control 2
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 Reserved
D5 R/W 0 0: DIN-to-DOUT loopback is disabled.
1: DIN-to-DOUT loopback is enabled.
D4 R/W 0 0: ADC-to-DAC loopback is disabled.
1: ADC-to-DAC loopback is enabled.
D3 R/W 0 0: BCLK is not inverted (valid for both primary and secondary BCLK).
1: BCLK is inverted (valid for both primary and secondary BCLK).
D2 R/W 0 BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary
BCLK)
0: Disabled
1: Enabled
D1–D0 R/W 00 00: BDIV_CLKIN = DAC_CLK (generated on-chip)
01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip)
10: BDIV_CLKIN = ADC_CLK (generated on-chip)
11: BDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
Page 0 / Register 30 (0x1E): BCLK N_VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: BCLK N-divider is powered down.
1: BCLK N-divider is powered up.
D6–D0 R/W 000 0001 000 0000: BCLK divider N = 128
000 0001: BCLK divider N = 1
000 0010: BCLK divider N = 2
...
111 1110: BCLK divider N = 126
111 1111: BCLK divider N = 127
Page 0 / Register 31 (0x1F): Codec Secondary Interface Control 1
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D5 R/W 000 000: Secondary BCLK is obtained from GPIO1 pin.
001: Reserved.
010: Reserved.
011: Secondary BCLK is obtained from DOUT pin.
100: Reserved.
101: Reserved.
110: Reserved.
111: Reserved.
D4–D2 R/W 000 000: Secondary WCLK is obtained from GPIO1 pin.
001: Reserved.
010: Reserved.
011: Secondary WCLK is obtained from DOUT pin.
100: Reserved.
101: Reserved.
110: Reserved.
111: Reserved.
D1–D0 R/W 00 00: Secondary DIN is obtained from the GPIO1 pin.
01: Reserved.
10: Reserved.
11: Reserved.
86 REGISTER MAP Copyright © 2009–2012, Texas Instruments Incorporated
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