Datasheet

TLV320AIC3110
www.ti.com SLAS647B –DECEMBER 2009–REVISED MAY 2012
Page 0 / Registers 25 (0x19): CLKOUT MUX
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D3 R/W 0000 0 Reserved
D2–D0 R/W 000 000: CDIV_CLKIN = MCLK (device pin)
001: CDIV_CLKIN = BCLK (device pin)
010: CDIV_CLKIN = DIN (can be used for the systems where DAC is not required)
011: CDIV_CLKIN = PLL_CLK (generated on-chip)
100: CDIV_CLKIN = DAC_CLK (generated on-chip)
101: CDIV_CLKIN = DAC_MOD_CLK (generated on-chip)
110: CDIV_CLKIN = ADC_CLK (generated on-chip)
111: CDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
Page 0 / Registers 26 (0x1A): CLKOUT M_VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: CLKOUT M divider is powered down.
1: CLKOUT M divider is powered up.
D6–D0 R/W 000 0001 000 0000: CLKOUT divider M = 128
000 0001: CLKOUT divider M = 1
000 0010: CLKOUT divider M = 2
...
111 1110: CLKOUT divider M = 126
111 1111: CLKOUT divider M = 127
Page 0 / Register 27 (0x1B): Codec Interface Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 00: Codec interface = I
2
S
DSP01: Codec Interface =
10: Codec interface = RJF
11: Codec interface = LJF
D5–D4 R/W 00 00: Codec interface word length = 16 bits
01: Codec interface word length = 20 bits
10: Codec interface word length = 24 bits
11: Codec interface word length = 32 bits
D3 R/W 0 0: BCLK is input.
1: BCLK is output.
D2 R/W 0 0: WCLK is input.
1: WCLK is output.
D1 R/W 0 Reserved
D0 R/W 0 Driving DOUT to High-Impedance for the Extra BCLK Cycle When Data Is Not Being Transferred
0: Disabled
1: Enabled
Page 0 / Register 28 (0x1C): Data-Slot Offset Programmability
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 Offset (Measured With Respect to WCLK Rising Edge in DSP Mode)
0000 0000: Offset = 0 BCLKs
0000 0001: Offset = 1 BCLK
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs
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