Datasheet
TLV320AIC3110
SLAS647B –DECEMBER 2009–REVISED MAY 2012
www.ti.com
Electrical Characteristics (continued)
At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD = SPRVDD = 3.6 V; DVDD = 1.8 V; f
S
(audio) = 48 kHz;
CODEC_CLKIN = 256 × f
S
; PLL = Off; VOL/MICDET pin disabled (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC Output to Class-D Speaker Output, Load = 8 Ω (Differential), 50 pF
SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM
= 1.8 V, DAC input = 0 dBFS, class-D gain = 6 dB, 2.2
THD ≤ –16.5 dB
Output voltage Vrms
SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM
= 1.8 V, DAC input = –2 dBFS, class-D gain = 6 dB, 2.1
THD ≤ –20 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement,
Output, common-mode 1.8 V
DAC input = mute, class-D gain = 6 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement,
class-D gain = 6 dB, measured as idle-channel noise,
SNR Signal-to-noise ratio 87 dB
A-weighted (with respect to full-scale output value of
2.2 Vrms)
(1) (2)
SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM
THD Total harmonic distortion –67 dB
= 1.8 V, DAC input = –6 dBFS, class-D gain = 6 dB
Total harmonic distortion + SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM
THD+N –66 dB
noise = 1.8 V, DAC input = –6 dBFS, class-D gain = 6 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement,
PSRR Power-supply rejection ratio
(3)
–44 dB
ripple on SPLVDD/SPRVDD = 200 mVp-p at 1 kHz
Mute attenuation 110 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM
540
= 1.8 V, class-D gain = 18 dB, THD = 10%
mW
SPLVDD = SPRVDD = 4.3 V, BTL measurement, CM
P
O
Maximum output power 790
= 1.8 V, class-D gain = 18 dB, THD = 10%
SPLVDD = SPRVDD = 5.5 V, BTL measurement, CM
1.29 W
= 1.8 V, class-D gain = 18 dB, THD = 10%
Output-stage leakage current SPLVDD = SPRVDD = 4.3 V, device is powered
80 nA
for direct battery connection down (power-up-reset condition)
ADC AND DAC POWER CONSUMPTION
For ADC and DAC power consumption based per selected processing block, see Section 5.3.
DIGITAL INPUT/OUTPUT
Logic family CMOS
0.7 ×
I
IH
= 5 μA, IOVDD ≥ 1.6 V
IOVDD
V
IH
V
I
IH
= 5 μA, IOVDD < 1.6 V IOVDD
0.3 ×
I
IL
= 5 μA, IOVDD ≥ 1.6 V –0.3
IOVDD
V
IL
V
Logic level
I
IL
= 5 μA, IOVDD < 1.6 V 0
0.8 ×
V
OH
I
OH
= 2 TTL loads V
IOVDD
0.1 ×
V
OL
I
OL
= 2 TTL loads V
IOVDD
Capacitive load 10 pF
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) DAC to speaker-out PSRR is a differential measurement calculated as PSRR = 20 × log(ΔV
SPL(P + M)
/ ΔV
SPLVDD
).
8 ELECTRICAL SPECIFICATIONS Copyright © 2009–2012, Texas Instruments Incorporated
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