Datasheet

BCLK
WCLK
DOUT
DOUT_int
S_DIN
BCLK
DIN
WCLK
DIN
DOUT
Primary
Audio
Processor
S_WCLK
DAC_f
S
ADC_f
S
S_BCLK
BCLK_OUT
BCLK
S_BCLK
WCLK
S_WCLK
DIN
S_DIN
WCLK
ADC_WCLK
Audio
Digital
Serial
Interface
BCLK_INT
DAC_WCLK_INT
ADC_WCLK_INT
DIN_INT
GPIO1
GPIO1
DOUT
DOUT
S_BCLK
BCLK
BCLK_OUT
S_WCLK
WCLK
DAC_f
S
ADC_f
S
GPIO1
S
_
DIN
DOUT_int
DIN
(S_DOUT)
Clock
Generation
BCLK_OUT
DAC_f
S
ADC_f
S
WCLK
DIN
DOUT
Secondary
Audio
Processor
BCLK
GPIO1
ADC_f
S
ADC_WCLK
BCLK2
WCLK2
GPIO1
TLV320AIC3110
SLAS647B –DECEMBER 2009–REVISED MAY 2012 www.ti.com
Table 5-44. Generation of ADC_WCLK (continued)
ADC_WCLK Possible
Page 0 Registers Comment
Direction Pins
R32/D7–D5 = 000 ADC_WCLK obtained from GPIO1 pin
INPUT GPIO1 R51/D5–D2 = 0001 GPIO1 enabled as secondary input
R32/D1 Select source of internal ADC_WCLK (0 = DAC_WCLK; 1 = ADC_WCLK)
Figure 5-51. Audio Serial Interface Multiplexing
5.7.3 Control Interface
The TLV320AIC3110 control interface supports the I
2
C communication protocol.
78 APPLICATION INFORMATION Copyright © 2009–2012, Texas Instruments Incorporated
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