Datasheet

Internal
Oscillator
÷8
0
1
P3/R16, Bits D6-D0
MCLK
P3/R16, Bit D7
Interval timers
Programmable
Divider
Powered on if
internal oscillator is
selected
Used for de-bounce time for
headset detection logic,
various power up timers and
for generation of interrupts
TLV320AIC3110
www.ti.com SLAS647B –DECEMBER 2009–REVISED MAY 2012
Figure 5-39. Interval Timer Clock Selection
5.7 Digital Audio and Control Interface
5.7.1 Digital Audio Interface
Audio data is transferred between the host processor and the TLV320AIC3110 via the digital audio data
serial interface, or audio bus. The audio bus on this device is very flexible, including left- or right-justified
data options, support for I
2
S or DSP protocols, programmable data-length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TLV320AIC3110 can be configured for left- or right-justified, I
2
S, DSP, or TDM
modes of operation, where communication with standard telephony interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0 / register 27, bits D5–D4. In addition, the word clock and bit clock can be
independently configured in either master or slave mode for flexible connectivity to a wide variety of
processors. The word clock is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0 / register 30 (see Figure 5-36). The number of bit-clock pulses in a frame may need adjustment
to accommodate various wordlengths as well as to support the case when multiple TLV320AIC3110s may
share the same audio bus.
The TLV320AIC3110 also includes a feature to offset the position of start of data transfer with respect to
the word clock. This offset can be controlled in terms of number of bit clocks and can be programmed in
page 0 / register 28.
The TLV320AIC3110 also has the feature of inverting the polarity of the bit clock used for transferring the
audio data as compared to the default clock polarity used. This feature can be used independently of the
mode of audio interface chosen. This can be configured via page 0 / register 29, bit D3.
Copyright © 2009–2012, Texas Instruments Incorporated APPLICATION INFORMATION 71
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