Datasheet

PLL _ CLKIN
512 kHz 20 MHz
P
£ £
PLL _ CLKIN R J.D
PLL _ CLK
P
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TLV320AIC3110
www.ti.com SLAS647B –DECEMBER 2009–REVISED MAY 2012
Table 5-41. Maximum TLV320AIC3110 Clock Frequencies
Clock DVDD ≥ 1.65 V
CODEC_CLKIN ≤ 110 MHz
ADC_CLK (ADC processing clock) ≤ 49.152 MHz
ADC_PRB_CLK ≤ 24.576 MHz
ADC_MOD_CLK 6.758 MHz
ADC_f
S
0.192 MHz
DAC_CLK (DAC processing clock) ≤ 49.152 MHz
DAC_PRB_CLK ≤ 49.152MHz with DRC disabled
≤ 48 MHz with DRC enabled
DAC_MOD_CLK 6.758 MHz
DAC_f
S
0.192 MHz
BDIV_CLKIN 55 MHz
CDIV_CLKIN 100 MHz when M is odd
110 MHz when M is even
5.6.1 PLL
For lower power consumption, it is best to derive the internal audio processing clocks using the simple
dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing
clocks then it is necessary to use the on-board PLL. The TLV320AIC3110 fractional PLL can be used to
generate an internal master clock used to produce the processing clocks needed by the ADC and DAC
and digital processing blocks. The programmability of this PLL allows operation from a wide variety of
clocks that may be available in the system.
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable
generation of the required sampling rates with fine resolution. The PLL can be turned on by writing to
page 0 / register 5, bit D7. When the PLL is enabled, the PLL output clock PLL_CLK is given by the
following equation:
(9)
where
R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)
J = 1, 2,3, …, 63, (page 0 / register 6, default value = 4)
D = 0, 1, 2, …, 9999 (page 0 / register 7 and 8, default value = 0)
P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1)
The PLL can be turned on via page 0 / register 5, bit D7. The variable P can be programmed via page 0 /
register 5, bits D6–D4. The variable R can be programmed via page 0 / register 5, bits D3–D0. The
variable J can be programmed via page 0 / register 6, bits D5–D0. The variable D is 14 bits and is
programmed into two registers. The MSB portion can be programmed via page 0 / register 7, bits D5–D0,
and the LSB portion is programmed via page 0 / register 8, bits D7–D0. For proper update of the D-divider
value, page 0 / register 7 must be programmed first followed immediately by page 0 / register 8. Unless
the write to page 0 / register 8 is completed, the new value of D will not take effect.
When the PLL is enabled the following conditions must be satisfied.
• When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
(10)
80 MHz ≤ (PLL_CLKIN × J.D × R/P) ≤ 110 MHz
4 ≤ R × J ≤ 259
Copyright © 2009–2012, Texas Instruments Incorporated APPLICATION INFORMATION 69
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