Datasheet
Audio Output Stage
Power Management
RC CLK
Digital
Audio
Processing
and
Serial
Interface
DOUT
DIN
BCLK
WCLK
MCLKPLL
7-Bit ADC P0/R116
Left and Right Volume-
Control Register
P0/R116
Digital Beep
Generator
Digital
Vol Ctl
Digital Vol
24 dB to
Mute
0 to –63 dB
(1-dB Steps)
Processing
Blocks
Processing
Blocks
PRB_R4–
PRB_R18
SPRP
SPRM
SPLP
SPLM
Class-D Speaker
Driver
6 dB to 24 dB (6-dB Steps)
Class A/B
Headphone/Lineout
Driver
0 dB to 9 dB (1-dB Steps)
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
Analog Attenuation
0 dB to –78 dB and Mute
(0.5-dB Steps / Nonlinear)
HPVDD
SPLVDD SPLVSS
AVDD
AVSSSPRVSSSPRVDD
VOL/
MICDET
HPR
HPL
SCL
SDA
GPIO GPIO1
MIX_R
MIX_L
MIX_R
MIX_L
MIC1LP
DAC_L
MIX_L
DAC_R
MIX_R
RESET
DVDD
DVSS
IOVDD IOVSS
OSC
RC CLK
MIC1LP
Selectable
Gain/Input
Impedance
VCOM
Selectable
Gain/Input
Impedance
P1/R47
0 to 59.5 dB
(0.5-dB steps)
AGC
MIC1RP
I C
2
2 V/2.5 V/AVDD
MICBIAS
Digital Vol
–12..20 dB
Step = 0.5 dB
Mono ADC
Note: Normally,
MCLK is PLL input;
however, BCLK,
GPIO1, etc., can
also be PLL input.
D S-
ADC
D S-
DAC
D S-
DAC
De-Pop
and
Soft-
Start
P1/R33–R34
S
S
S
S
S
S
S
S
P1/R42
P1/R38
P1/R43
P1/R39
P1/R32
P0/R63
P1/R30
P1/R40
P1/R41
P1/R31
P1/R44
P1/R36
P1/R37
P1/R35
P0/R71
P0/R72
P0/R86–R93
P1/R48
P1/R49
Input CM
P1/R50
B0205-07
P0/
R64–R65
P0/R82–R83
HPVSS
MIC1RP
MIC1LM
PRB_P1–
PRB_P25
TLV320AIC3110
SLAS647B –DECEMBER 2009–REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Figure 1-1. Functional Block Diagram
2 INTRODUCTION Copyright © 2009–2012, Texas Instruments Incorporated
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