Datasheet
TLV320AIC3106
SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 ........................................................................................................................................
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Page 0 / Register 107: New Programmable ADC Digital Path and I
2
C Bus Condition Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Left Channel High Pass Filter Coefficient Selection
0: Default Coefficients are used when ADC High Pass is enabled.
1: Programmable Coefficients are used when ADC High Pass is enabled.
D6 R/W 0 Right Channel High Pass Filter Coefficient Selection
0: Default Coefficients are used when ADC High Pass is enabled.
1: Programmable Coefficients are used when ADC High Pass is enabled.
D5 – D4 R/W 00 ADC Decimation Filter configuration
00: Left and Right Digital Microphones are used
01: Left Digital Microphone and Right Analog Microphone are used
10: Left Analog Microphone and Right Digital Microphone are used
11: Left and Right Analog Microphones are used
D3 R/W 0 ADC Digital output to Programmable Filter Path Selection
0: No additional Programmable Filters other than the HPF are used for the ADC.
1: The Programmable Filter is connected to ADC output, if both DACs are powered down.
D2 R/W 0 I
2
C Bus Condition Detector
0: Internal logic is enabled to detect an I
2
C bus error, and clears the bus error condition.
1: Internal logic is disabled to detect an I
2
C bus error.
D1 R 0 Reserved. Write only zero to these register bits.
D0 R 0 I
2
C Bus error detection status
0: I
2
C bus error is not detected
1: I
2
C bus error is detected. This bit is cleared by reading this register.
Page 0 / Register 108: Passive Analog Signal Bypass Selection During Powerdown Register
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 LINE2RM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOM
D6 R/W 0 LINE2RP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOP
D5 R/W 0 LINE1RM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOM
D4 R/W 0 LINE1RP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to RIGHT_LOP
D3 R/W 0 LINE2LM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOM
D2 R/W 0 LINE2LP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOP
D1 R/W 0 LINE1LM Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOM
D0 R/W 0 LINE1LP Path Selection
0: Normal Signal Path
1: Signal is routed by a switch to LEFT_LOP
(1) Based on the setting above, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches used for
the connection short the two input signals together on the output pins. The shorting resistance between the two input pins is two times
the bypass switch resistance (Rdson). In general this condition of shorting should be avoided, as higher drive currents are likely to occur
on the circuitry that feeds these two input pins of this device.
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