Datasheet

Volume0dBto
+9dB,mute
Volume0dBto
+9dB,mute
VCM
Volume0dBto
+9dB,mute
Volume0dB
to+9dB,
mute
VCM
HPLOUT
HPLCOM
HPROUT
HPRCOM
DAC_L2
LINE2L
LINE2R
PGA_L
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
PGA_R
DAC_R2
LINE2L
LINE2R
PGA_L
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
PGA_R
LINE2L
LINE2R
PGA_L
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
PGA_R
LINE2L
LINE2R
PGA_L
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
PGA_R
TLV320AIC3106
www.ti.com ........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008
The output stage architecture leading to the high power output drivers is shown in Figure 36 , with the volume
control and mixing blocks being effectively identical to that shown in Figure 35 . Note that each of these drivers
have a output level control block like those included with the line output drivers, allowing gain adjustment up to
+9dB on the output signal. As in the previous case, this output level adjustment is not intended to be used as a
standard volume control, but instead is included for additional fullscale output signal level control.
Two of the output drivers, HPROUT and HPLOUT, include a direct connection path for the stereo DAC outputs to
be passed directly to the output drivers and bypass the analog volume controls and mixing networks, using the
DAC_L2/R2 path. As in the line output case, this functionality provides the highest quality DAC playback
performance with reduced power dissipation, but can only be utilized if the DAC output does not need to route to
multiple output drivers simultaneously, and if mixing of the DAC output with other analog signals is not needed.
Figure 36. Architecture of the Output Stage Leading to the High Power Output Drivers
The high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on
and power-off transient conditions. The user should first program the type of output configuration being used in
Page-0/Reg-14, to allow the device to select the optimal power-up scheme to avoid output artifacts. The
power-up delay time for the high power output drivers is also programmable over a wide range of time delays,
from instantaneous up to 4-sec, using Page-0/Reg-42.
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