Datasheet

PIN ASSIGNMENTS
A
1 2 3 4
5
6
7
8 9
B
C
D
E
F
G
H
J
48−leadQFNPackage
(BottomView)
5x5mm80−BallBGA Package
(BottomView)
48
1
12
13
24
25
36
37
(Nottoscale)
TLV320AIC3106
SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008 ........................................................................................................................................ www.ti.com
Solder the QFN thermal pad to the ground plane (DRVSS).
The shaded balls on BGA package are not connected to the die, but are electrically connected to each other.
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
BGA BALL QFN NAME
A2 13 MICBIAS Microphone bias voltage output
A1 14 MIC3R MIC3 input (right or multifunction)
C2,D2 15 AVSS_ADC Analog ADC ground supply, 0 V
B1,C1 16,17 DRVDD ADC analog and output driver voltage supply, 2.7 V – 3.6 V
D1 18 HPLOUT High-power output driver (left +)
E1 19 HPLCOM High-power output driver (left – or multifunctional)
E2,F2 20,21 DRVSS Analog output driver ground supply, 0 V
F1 22 HPRCOM High-power output driver (right – or multifunctional)
G1 23 HPROUT High-power output driver (right +)
H1 24 DRVDD ADC analog and output driver voltage supply, 2.7 V – 3.6 V
J1 25 AVDD_DAC Analog DAC voltage supply, 2.7 V – 3.6 V
G2,H2 26 AVSS_DAC Analog DAC ground supply, 0 V
J2 27 MONO_LOP Mono line output (+)
J3 28 MONO_LOM Mono line output ( – )
J4 29 LEFT_LOP Left line output (+)
J5 30 LEFT_LOM Left line output ( – )
J6 31 RIGHT_LOP Right line output (+)
J7 32 RIGHT_LOM Right line output ( – )
H8 33 RESET Reset
General-purpose input/output #2 (input/output)/digital microphone data input/PLL clock
J8 34 GPIO2
input/audio serial data bus bit clock input/output
4 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3106