Datasheet

STEREO AUDIO ADC
TLV320AIC3106
www.ti.com ........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008
8.192 1 1 12 0 48000.00 0.0000
12.0 1 1 8 1920 48000.00 0.0000
13.0 1 1 7 5618 47999.71 – 0.0006
16.0 1 1 6 1440 48000.00 0.0000
19.2 1 1 5 1200 48000.00 0.0000
19.68 1 1 4 9951 47999.79 – 0.0004
48.0 4 1 8 1920 48000.00 0.0000
The TLV320AIC3106 can also output a separate clock on the GPIO1 pin. If the PLL is being used for the audio
data converter clock, the M and N settings can be used to provide a divided version of the PLL output. If the PLL
is not being used for the audio data converter clock, the PLL can still be enabled to provide a completely
independent clock output on GPIO1. The formula for the GPIO1 clock output when PLL is enabled and
CLKMUX_OUT is 0 is:
GPIO1 = (PLLCLK_IN × 2 × K × R) / (M × N × P)
When CLKMUX_OUT is 1, regardless of whether PLL is enabled or disabled, the input to the clock output divider
can be selected as MCLK, BCLK, or GPIO2. Is this case, the formula for the GPIO1 clock is:
GPIO1 = (CLKDIV_IN × 2) / (M × N), where
M = 1, 2, 4, 8
N = 2, 3, … , 17
CLKDIV_IN can be BCLK, MCLK, or GPIO2, selected by page 0, register 102, bits D7-D6
The TLV320AIC3106 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8
kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in
operation, the device requires that an audio master clock be provided and appropriate audio clock generation be
set up within the device.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support the case where only mono record capability is required. In addition, both channels can be fully powered
or entirely powered down.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 f
S
to the final output sampling rate of f
S
. The decimation filter provides a linear phase
output response with a group delay of 17/f
S
. The – 3-dB bandwidth of the decimation filter extends to 0.45 f
S
and
scales with the sample rate (f
S
). The filter has minimum 75-dB attenuation over the stop band from 0.55 f
S
to 64
f
S
. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that
can be independently set.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3106 integrates a second-order
analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient antialiasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part
after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC
power-down flag is no longer set, the audio master clock can be shut down.
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