Datasheet
DA(6) DA(0) RA(7) RA(0) D(7) D(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
8-bit Register Data
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
DA(6) DA(0) RA(7) RA(0)
Start
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
SDA
SCL
DA(6) DA(0)
7-bit Device Address
(M)
Read
(M)
Slave
Ack
(S)
D(7) D(0)
8-bit Register Data
(S)
Stop
(M)
Master
No Ack
(M)
Repeat
Start
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
I
2
C BUS DEBUG IN A GLITCHED SYSTEM
DIGITAL AUDIO DATA SERIAL INTERFACE
TLV320AIC3106
www.ti.com
........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it will receive a not − acknowledge because no device
is present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320AIC3106 also responds to and acknowledges a General Call, which consists of the master issuing a
command with a slave address byte of 00H.
Figure 17. I
2
C Write
Figure 18. I
2
C Read
In the case of an I
2
C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental
register.
Similarly, in the case of an I
2
C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the
next 8 clocks the data of the next incremental register.
Occasionally, some systems may encounter noise or glitches on the I
2
C bus. In the unlikely event that this
affects bus performance, then it can be useful to use the I
2
C Debug register. This feature terminates the I
2
C bus
error allowing this I
2
C device and system to resume communications. The I
2
C bus error detector is enabled by
default. The TLV320AIC3106 I
2
C error detector status can be read from Page 0, Register 107, bit D0. If desired,
the detector can be disabled by writing to Page 0, Register 107, bit D2.
Audio data is transferred between the host processor and the TLV320AIC3106 via the digital audio data serial
interface, or audio bus. The audio bus on this device is very flexible, including left or right justified data options,
support for I
2
S or PCM protocols, programmable data length options, a TDM mode for multichannel operation,
very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple
devices within a system directly.
The data serial interface uses two sets of pins for communication between external devices, with the particular
pin used controlled through register programming. This configuration is shown in Figure 19 below.
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