Datasheet

OVERVIEW
HARDWARE RESET
DIGITAL CONTROL SERIAL INTERFACE
SPI CONTROL MODE
RA(6) RA(5) RA(0) D(7) D(6) D(0)
7-bitRegister Address
Write 8-bitRegisterData
SS
SCLK
MOSI
MISO
Hi-Z Hi-Z
Hi-Z Hi-Z
TLV320AIC3106
www.ti.com ........................................................................................................................................ SLAS509E – DECEMBER 2006 – REVISED DECEMBER 2008
The TLV320AIC3106 is a highly flexible, low power, stereo audio codec with extensive feature integration,
intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment
applications. Available in a 5x5mm 80-ball BGA (with 51 balls actually used) and 7x7mm 48-lead QFN, the
product integrates a host of features to reduce cost, board space, and power consumption in space-constrained,
battery-powered, portable applications.
The TLV320AIC3106 consists of the following blocks:
• Stereo audio multi-bit delta-sigma DAC (8 kHz – 96 kHz)
• Stereo audio multi-bit delta-sigma ADC (8 kHz – 96 kHz)
• Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, notch filter, de-emphasis)
• Six audio inputs
• Four high-power audio output drivers (headphone drive capability)
• Three fully differential line output drivers
• Fully programmable PLL
• Headphone/headset jack detection with interrupt
Communication to the TLV320AIC3106 for control is pin-selectable (using the SELECT pin) as either SPI or I
2
C.
The SPI interface requires that the Slave Select signal (MFP0) be driven low to communicate with the
TLV320AIC3106. Data is then shifted into or out of the TLV320AIC3106 under control of the host
microprocessor, which also provides the serial data clock. The I
2
C interface supports both standard and fast
communication modes, and also enables cascading of up to four multiple codecs on the same I
2
C bus through
the use of two pins for addressing (MFP0, MFP1).
The TLV320AIC3106 requires a hardware reset after power-up for proper operation. After all power supplies are
at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320AIC3106 may not respond properly to register reads/writes.
The TLV320AIC3106 control interface supports SPI or I
2
C communication protocols, with the protocol selectable
using the SELECT pin. For SPI, SELECT should be tied high; for I
2
C, SELECT should be tied low. It is not
recommended to change the state of SELECT during device operation.
Figure 14. SPI Write
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