Datasheet

TLV320AIC3104
SLAS510C –FEBRUARY 2007–REVISED DECEMBER 2010 www.ti.com
Table 73. Page 0/Register 107: New Programmable ADC Digital Path and I
2
C Bus Condition Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Left-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
D6 R/W 0 Right-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
D5–D4 R/W 00 ADC Decimation Filter Configuration
00: Reserved
01: Reserved
10: Reserved
11: Left and right analog microphones are used.
D3 R/W 0 ADC Digital Output to Programmable Filter Path Selection
0: No additional programmable filters other than the HPF are used for the ADC.
1: The programmable filter is connected to ADC output, if both DACs are powered down.
D2 R/W 0 I
2
C Bus Condition Detector
0: Internal logic is enabled to detect an I
2
C bus error, and clears the bus error condition.
1: Internal logic is disabled to detect an I
2
C bus error.
D1 R 0 Reserved. Write only zero to these register bits.
D0 R 0 I
2
C Bus Error Detection Status
0: I
2
C bus error is not detected.
1: I
2
C bus error is detected. This bit is cleared by reading this register.
Table 74. Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down Register
(1)
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved. Write only zero to this bit.
D6 R/W 0 LINE2RP Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP.
D5 R/W 0 LINE1RM Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM.
D4 R/W 0 LINE1RP Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP.
D3 R/W 0 Reserved. Write only zero to this bit.
D2 R/W 0 LINE2LP Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP.
D1 R/W 0 LINE1LM Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM.
D0 R/W 0 LINE1LP Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP.
(1) Based on the register 108 settings, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches
used for the connection short the two input signals together on the output pins. The shorting resistance between the two input pins is
two times the bypass switch resistance (Rdson). In general, this condition of shorting should be avoided, as higher drive currents are
likely to occur on the circuitry that feeds these two input pins of this device.
Table 75. Page 0/Register 109: DAC Quiescent Current Adjustment Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 DAC Current Adjustment
00: Default
01: 50% increase in DAC reference current
10: Reserved
11: 100% increase in DAC reference current
D5–D0 R/W 00 0000 Reserved. Write only zeros to these bits.
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